Nanometer Frequency Synthesis Beyond the Phase-Locked Loop

LIMING XIU is Chief Clock Architect at the Novatek Microelectronics Corporation and formerly a senior member of the technical staff at Texas Instruments Inc. Xiu served as vice president of the IEEE Circuits and System Society during 2009–2010. He has written numerous journal and conference papers, holds a number of patents, and is the author of VLSI Circuit Design Methodology Demystified from Wiley-IEEE Press.

• PREFACE xi 1 CLOCK SIGNAL IN ELECTRONIC SYSTEMS 11.1 The Significance of Clock Signal 11.2 The Characteristics of Clock Signal 51.3 Clock Signal Driving Digital System 181.4 Clock Signal Driving Sampling System 241.5 Extracting Clock Signal From Data: Clock Data Recovery 301.6 Clock Usage in System-on-Chip 321.7 Two Fields: Clock Generation and Clock Distribution 332 CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES 372.1 Direct Analog Frequency Synthesis 382.2 Direct Digital Frequency Synthesis 392.3 Indirect Method (Phase-Locked Loop Based) 412.4 The Shared Goal: All Cycles Have Same Length-in-Time 513 TIME-AVERAGE-FREQUENCY 533.1 The Scale of Level and the Scale of Time 533.2 What Is Frequency? 543.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency 563.4 Time-Average-Frequency in Circuit Implementation 593.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency 613.6 The Need of a Theory 623.7 The Summary: Why Do We Need Time-Average-Frequency? 634 FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE 654.1 The Working Principle 654.2 The Major Challenges in the Flying-Adder Circuit 684.3 The Circuit of Proof of Concept 744.4 The Working Circuitry 774.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed 874.6 The Technique of Post Divider Fractional Bits Recovery 884.7 Flying-Adder PLL: FAPLL 904.8 Flying-Adder Fractional Divider 914.9 Integer-Flying-Adder Architecture 924.10 The Algorithm to Search Optimum Parameters 984.11 The Construction of the Accumulator 994.12 The Construction of the High Speed Multiplex 1044.13 Non-2’s Power Flying-Adder Circuit 1074.14 Expanding VCO Frequency Range in Nanometer CMOS Processes 1094.15 Multiple Flying-Adder Synthesizers 1104.16 Flying-Adder Implementation Styles 1114.17 Simulation Approaches 1124.18 The Impact of Input Mismatch on Output Jitter 1134.19 Flying-Adder Circuit as Digital Controlled Oscillator 1274.20 Flying-Adder Terminology 1284.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence 1294.22 Time-Average-Frequency and Setup Constraint: Revisit 1544.23 Sense the Frequency Difference: The Time-Average-Frequency Way 1564.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference 1574.25 Flying-Adder for Phase (Delay) Synthesis 1584.26 Flying-Adder for Duty Cycle Control 1624.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC 1635 DIGITAL-TO-FREQUENCY CONVERTER 1675.1 Two Ways of Representing Information 1675.2 The Converters for Transforming Information 1685.3 The Two Cornerstones of the Digital-to-Frequency Converter 1705.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter 1725.5 Convert the Spurious Energy to Noise Energy 1935.6 Move Spurs Around 1985.7 Spread the Energy 2015.8 Performance Merits 2056 THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN 2116.1 The Clocking Challenges in Reality 2116.2 Flying-Adder and Its Three Major Application Areas 2166.3 Flying-Adder for On-chip Frequency Generation 2186.4 Flying-Adder as Adaptive Clock Generator 2226.5 Flying-Adder as On-chip VCXO 2306.6 Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation 2376.7 Flying-Adder for Frequency Synchronization in Digital Communication: A Preview 2406.8 Flying-Adder for Clock Data Recovery 2426.9 Flying-Adder DLL for Deskew 2556.10 Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL) 2566.11 Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL) 2626.12 Flying-Adder Technology for Dynamic Frequency Scaling 2626.13 Flying-Adder as 1-bit DDFS 2646.14 Flying-Adder for Spread Spectrum Clocking 2656.15 Flying-Adder for Driving Sampling System 2686.16 Flying-Adder for Non-uniform Sampling 2716.17 Flying-Adder as Digital FSK Modulator 2736.18 Flying-Adder for PWM/PFW DC-DC Power Conversion 2746.19 Integrate Clocking Chips into Processing Chips 2757 LOOKING INTO FUTURE: THE ERA OF "TIME" 2797.1 The Four Fundamental Technologies in Modern Chip Design 2797.2 "Time"-Based Analog Processing 2817.3 "Time" and Frequency: Encoding Messages Through Modulation 2837.4 Manipulate "Time": The Tools 2837.5 It Is Time to Use "Time" 284APPENDICES 287Appendix 4.A: The VHDL Code for Flying-Adder Synthesizer 287Appendix 4.B: How Close Can It Reach an Integer? 296Appendix 4.C: The Seed and Set in Integer-Flying-Adder PLL 299Appendix 4.D: The Number of Carries From an XIU-Accumulator 302Appendix 5.A: The Flying-Adder State Machine Model (perl) 303Appendix 5.B: The Flying-Adder Waveform Generator (perl) 307Appendix 5.C: The Flying-Adder Waveform Generator with Triangular Modulation (perl) 310Appendix 5.D: The Flying-Adder Waveform Generator with Random Modulation (perl) 314Appendix 6.A: The FA-DCXO Tangent Line and Linearity Measurement 318INDEX 321