CMOS

R. JACOB (JAKE) BAKER, PHD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds more than 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books for Wiley-IEEE Press. In 2007, he received the Hewlett-Packard Frederick Emmons Terman Award.

• Preface xxxiiiChapter 1 Introduction to CMOS Design 11.1 The CMOS IC Design Process 11.1.1 Fabrication 21.2 CMOS Background 51.3 An Introduction to SPICE 8Chapter 2 The Well 312.1 Patterning 322.1.1 Patterning the N-well 352.2 Laying Out the N-well 352.2.1 Design Rules for the N-well 362.3 Resistance Calculation 362.3.1 The N-well Resistor 382.4 The N-well/Substrate Diode 392.4.1 A Brief Introduction to PN Junction Physics 392.4.2 Depletion Layer Capacitance 422.4.3 Storage or Diffusion Capacitance 452.4.4 SPICE Modeling 462.5 The RC Delay through the N-well 482.6 Twin Well Processes 51Chapter 3 The Metal Layers 593.1 The Bonding Pad 593.1.1 Laying Out the Pad I 603.2 Design and Layout Using the Metal Layers 633.2.1 Metal1 and Via1 633.2.2 Parasitics Associated with the Metal Layers 633.2.3 Current-Carrying Limitations 673.2.4 Design Rules for the Metal Layers 683.2.5 Contact Resistance 693.3 Crosstalk and Ground Bounce 703.3.1 Crosstalk 713.3.2 Ground Bounce 723.4 Layout Examples 743.4.1 Laying Out the Pad II 743.4.2 Laying Out Metal Test Structures 76Chapter 4 The Active and Poly Layers 834.1 Layout Using the Active and Poly Layers 834.1.1 Process Flow 904.2 Connecting Wires to Poly and Active 934.3 Electrostatic Discharge (ESD) Protection 99Chapter 5 Resistors, Capacitors, MOSFETs 1075.1 Resistors 1075.2 Capacitors 1155.3 MOSFETs 1185.4 Layout Examples 125Chapter 6 MOSFET Operation 1356.1 MOSFET Capacitance Overview/Review 1366.2 The Threshold Voltage 1396.3 IV Characteristics of MOSFETs 1446.3.1 MOSFET Operation in the Triode Region 1446.3.2 The Saturation Region 1466.4 SPICE Modeling of the MOSFET 1496.4.1 Some SPICE Simulation Examples 1516.4.2 The Subthreshold Current 1526.5 Short-Channel MOSFETs 1546.5.1 MOSFET Scaling 1556.5.2 Short-Channel Effects 1566.5.3 SPICE Models for Our Short-Channel CMOS Process 157Chapter 7 CMOS Fabrication by Jeff Jessing 1657.1 CMOS Unit Processes 1657.1.1 Wafer Manufacture 1657.1.2 Thermal Oxidation 1677.1.3 Doping Processes 1687.1.4 Photolithography 1707.1.5 Thin Film Removal 1737.1.6 Thin Film Deposition 1777.2 CMOS Process Integration 1807.2.1 Frontend-of-the-Line Integration 1827.2.2 Backend-of-the-Line Integration 1967.3 Backend Processes 2107.4 Advanced CMOS Process Integration 2127.4.1 FinFETs 2137.4.2 Dual Damascene Low-k/Cu Interconnects 2167.5 Summary 219Chapter 8 Electrical Noise: An Overview 2218.1 Signals 2218.1.1 Power and Energy 2218.1.2 Power Spectral Density 2238.2 Circuit Noise 2268.2.1 Calculating and Modeling Circuit Noise 2278.2.2 Thermal Noise 2318.2.3 Signal-to-Noise Ratio 2378.2.4 Shot Noise 2478.2.5 Flicker Noise 2518.2.6 Other Noise Sources 2588.3 Discussion 2608.3.1 Correlation 2608.3.2 Noise and Feedback 2648.3.3 Some Final Notes Concerning Notation 267Chapter 9 Models for Analog Design 2779.1 Long-Channel MOSFETs 2779.1.1 The Square-Law Equations 2799.1.2 Small Signal Models 2869.1.3 Temperature Effects 3009.2 Short-Channel MOSFETs 3029.2.1 General Design (A Starting Point) 3039.2.2 Specific Design (A Discussion) 3069.3 MOSFET Noise Modeling 308Chapter 10 Models for Digital Design 32710.1 The Digital MOSFET Model 32810.1.2 Process Characteristic Time Constant 33110.1.3 Delay and Transition Times 33310.1.4 General Digital Design 32610.2 The MOSFET Pass Gate 32610.2.1 Delay through a Pass Gate 33810.2.2 Delay through Series-Connected PGs 34010.3 A Final Comment Concerning Measurements 341Chapter 11 The Inverter 34711.1 DC Characteristics 34711.2 Switching Characteristics 35211.3 Layout of the Inverter 35611.4 Sizing for Large Capacitive Loads 35811.5 Other Inverter Configurations 364Chapter 12 Static Logic Gates 36912.1 DC Characteristics of the NAND and NOR Gates 36912.1.1 DC Characteristics of the NAND Gate 36912.1.2 DC Characteristics of the NOR Gate 37212.2 Layout of the NAND and NOR Gates 37312.3 Switching Characteristics 37412.3.1 NAND Gate 37512.3.2 Number of Inputs 37812.4 Complex CMOS Logic Gates 379Chapter 13 Clocked Circuits 38913.1 The CMOS TG 38913.2 Applications of the Transmission Gate 39113.3 Latches and Flip-Flops 39513.4 Examples 402Chapter 14 Dynamic Logic Gates 41114.1 Fundamentals of Dynamic Logic 41114.1.1 Charge Leakage 41114.1.2 Simulating Dynamic Circuits 41414.1.3 Nonoverlapping Clock Generation 41514.1.4 CMOS TG in Dynamic Circuits 41614.2 Clocked CMOS Logic 417Chapter 15 CMOS Layout Examples 42515.1 Chip Layout 42615.2 Layout Steps by Dean Moriarty 434Chapter 16 Memory Circuits 44516.1 Array Architectures 44616.1.1 Sensing Basics 44616.1.2 The Folded Array 45216.1.3 Chip Organization 45816.2 Peripheral Circuits 45816.2.1 Sense Amplifier Design 45816.2.2 Row/Column Decoders 46716.2.3 Row Drivers 47016.3 Memory Cells 47116.3.1 The SRAM Cell 47316.3.2 Read-Only Memory (ROM) 47316.3.3 Floating Gate Memory 473Chapter 17 Sensing Using Modulation 49317.1 Qualitative Discussion 49417.1.1 Examples of DSM 49417.1.2 Using DSM for Sensing in Flash Memory 49617.2 Sensing Resistive Memory 50617.3 Sensing in CMOS Imagers 513Chapter 18 Special Purpose CMOS Circuits 53318.1 The Schmitt Trigger 53318.1.1 Design of the Schmitt Trigger 53418.1.2 Applications of the Schmitt Trigger 53618.2 Multivibrator Circuits 53818.2.1 The Monostable Multivibrator 53918.2.2 The Astable Multivibrator 54018.3 Input Buffers 54118.3.1 Basic Circuits 54118.3.2 Differential Circuits 54318.3.3 DC Reference 54718.3.4 Reducing Buffer Input Resistance 55018.4 Charge Pumps (Voltage Generators) 55118.4.1 Increasing the Output Voltage 55318.4.2 Generating Higher Voltages: The Dickson Charge Pump 55318.4.3 Example 556Chapter 19 Digital Phase-Locked Loops 56119.1 The Phase Detector 56319.1.1 The XOR Phase Detector 56319.1.2 The Phase Frequency Detector 56719.2 The Voltage-Controlled Oscillator 57019.2.1 The Current-Starved VCO 57019.2.2 Source-Coupled VCOs 57419.3 The Loop Filter 57619.3.1 XOR DPLL 57719.3.2 PFD DPLL 58319.4 System Concerns 59019.4.1 Clock Recovery from NRZ Data 59319.5 Delay-Locked Loops 60019.6 Some Examples 60319.6.1 A 2 GHz DLL 60319.6.2 A 1 Gbit/s Clock-Recovery Circuit 609Chapter 20 Current Mirrors 62120.1 The Basic Current Mirror 62120.1.1 Long-Channel Design 62220.1.2 Matching Currents in the Mirror 62420.1.3 Biasing the Current Mirror 62820.1.4 Short-Channel Design 63420.1.5 Temperature Behavior 63820.1.6 Biasing in the Subthreshold Region 64220.2 Cascoding the Current Mirror 64320.2.1 The Simple Cascode 64320.2.2 Low-Voltage (Wide-Swing) Cascode 64520.2.3 Wide-Swing, Short-Channel Design 64820.2.4 Regulated Drain Current Mirror 65120.3 Biasing Circuits 65320.3.1 Long-Channel Biasing Circuits 65320.3.2 Short-Channel Biasing Circuits 65620.3.3 A Final Comment 657Chapter 21 Amplifiers 67121.1 Gate-Drain Connected Loads 67121.1.1 Common-Source (CS) Amplifiers 67121.1.2 The Source Follower (Common-Drain Amplifier) 68321.1.3 Common Gate Amplifier 68421.2 Current Source Loads 68521.2.1 Common-Source Amplifier 68521.2.2 The Cascode Amplifier 69821.2.3 The Common-Gate Amplifier 70221.2.4 The Source Follower (Common-Drain Amplifier) 70221.3 The Push-Pull Amplifier 71021.3.1 DC Operation and Biasing 71121.3.2 Small-Signal Analysis 71421.3.3 Distortion 716Chapter 22 Differential Amplifiers 73522.1 The Source-Coupled Pair 73522.1.1 DC Operation 73522.1.2 AC Operation 74122.1.3 Common-Mode Rejection Ratio 74522.1.4 Matching Considerations 74622.1.5 Noise Performance 74922.1.6 Slew-Rate Limitations 75022.2 The Source Cross-Coupled Pair 75022.2.1 Current Source Load 75422.3 Cascode Loads (The Telescopic Diff-Amp) 75622.4 Wide-Swing Differential Amplifiers 75822.4.1 Current Differential Amplifier 76022.4.2 Constant Transconductance Diff-Amp 760Chapter 23 Voltage References 77323.1 MOSFET-Resistor Voltage References 77423.1.1 The Resistor-MOSFET Divider 77423.1.2 The MOSFET-Only Voltage Divider 77723.1.3 Self-Biased Voltage References 77823.2 Parasitic Diode-Based References 78423.2.1 Long-Channel BGR Design 78723.2.2 Short-Channel BGR Design 795Chapter 24 Operational Amplifiers I 80324.1 The Two-Stage Op-Amp 80424.2 An Op-Amp with Output Buffer 82224.3 The Operational Transconductance Amplifier (OTA) 82424.4 Gain-Enhancement 83524.5 Some Examples and Discussions 839Chapter 25 Dynamic Analog Circuits 85725.1 The MOSFET Switch 85725.1.1 Sample-and-Hold Circuits 86125.2 Fully-Differential Circuits 86425.2.1 A Fully-Differential Sample-and-Hold 86625.3 Switched-Capacitor Circuits 86925.3.1 Switched-Capacitor Integrator 87125.4 Circuits 879Chapter 26 Operational Amplifiers II 88926.1 Biasing for Power and Speed 88926.1.1 Device Characteristics 89026.1.2 Biasing Circuit 89126.2 Basic Concepts 89226.3 Basic Op-Amp Design 90026.4 Op-Amp Design Using Switched-Capacitor CMFB 920Chapter 27 Nonlinear Analog Circuits 93327.1 Basic CMOS Comparator Design 93327.1.1 Characterizing the Comparator 93927.1.2 Clocked Comparators 94227.1.3 Input Buffers Revisited 94327.2 Adaptive Biasing 94327.3 Analog Multipliers 94627.3.1 The Multiplying Quad 947Chapter 28 Data Converter Fundamentals by Harry Li 95528.1 Analog Versus Discrete Time Signals 95528.2 Converting Analog Signals to Digital Signals 95628.3 Sample-and-Hold (S/H) Characteristics 95928.4 Digital-to-Analog Converter (DAC) Specifications 96128.5 Analog-to-Digital Converter (ADC) Specifications 97028.6 Mixed-Signal Layout Issues 979Chapter 29 Data Converter Architectures by Harry Li 98729.1 DAC Architectures 98729.1.1 Digital Input Code 98729.1.2 Resistor String 98729.1.3 R-2R Ladder Networks 99229.1.4 Current Steering 99529.1.5 Charge-Scaling DACs 99929.1.6 Cyclic DAC 100329.1.7 Pipeline DAC 100529.2 ADC Architectures 100629.2.1 Flash 100629.2.2 The Two-Step Flash ADC 101029.2.3 The Pipeline ADC 101429.2.4 Integrating ADCs 101829.2.5 The Successive Approximation ADC 102229.2.6 The Oversampling ADC 1027Chapter 30 Implementing Data Converters 104330.1 R-2R Topologies for DACs 104330.1.1 The Current-Mode R-2R DAC 104430.1.2 The Voltage-Mode R-2R DAC 104530.1.3 A Wide-Swing Current-Mode R-2R DAC 104730.1.4 Topologies Without an Op-Amp 105730.2 Op-Amps in Data Converters 106330.2.1 Op-Amp Gain 106630.2.2 Op-Amp Unity Gain Frequency 106730.2.3 Op-Amp Offset 106730.3 Implementing ADCs 107030.3.1 Implementing the S/H 107130.3.2 The Cyclic ADC 107730.3.3 The Pipeline ADC 1084Chapter 31 Feedback Amplifiers with Harry Li 111531.1 The Feedback Equation 111531.2 Properties of Negative Feedback on Amplifier Design 111731.2.1 Gain Desensitivity 111731.3 Recognizing Feedback Topologies 112031.3.1 Input Mixing 112131.3.2 Output Sampling 112131.3.3 The Feedback Network 112231.3.4 Calculating Open-Loop Parameters 112531.3.5 Calculating Closed-Loop Parameters 112731.4 The Voltage Amp (Series-Shunt Feedback) 112831.5 The Transimpedance Amp (Shunt-Shunt Feedback) 113431.5.1 Simple Feedback Using a Gate-Drain Resistor 114031.6 The Transconductance Amp (Series-Series Feedback) 114231.7 The Current Amplifier (Shunt-Series Feedback) 114631.8 Stability 114831.8.1 The Return Ratio 115131.9 Design Examples 115431.9.1 Voltage Amplifiers 115431.9.2 A Transimpedance Amplifier 1158Chapter 32 Hysteretic Power Converters 117532.1 A Review of Power and Energy Basics 117632.1.1 Energy Storage in Inductors and Capacitors 117732.1.2 Energy Use in Transmitting Data 118032.1.3 Selection and use of Switches 118132.2 Switching Power Supplies: Some Examples 118932.2.1 The Buck SPS 118932.2.2 The Boost SPS 119632.2.3 The Flyback SPS 120032.2.4 Pulse Width Modulation: A Control Loop Example 120432.3 Hysteretic Control 121032.3.1 Topologies 121132.3.2 Examples 1212Index 1219About the Author 1235