3D IC Integration and Packaging

John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects. John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Who’s Who in America.

• 1 3D Integration for Semiconductor IC Packaging1.1 Introduction1.2 3D Integration1.3 3D IC Packaging1.4 3D Si Integration1.5 3D IC Integration1.5.1 Hybrid Memory Cube1.5.2 Wide I/O DRAM and Wide I/O 21.5.3 High Bandwidth Memory1.5.4 Wide I/O Memory (or Logic-on-Logic)1.5.5 Passive Interposer (2.5D IC Integration)1.6 Supply Chains before the TSV Era1.6.1 FEOL (Front-End-of-Line)1.6.2 BEOL (Back-End-of-Line)1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)1.7 Supply Chains for the TSV Era—Who Makes the TSV?1.7.1 TSVs Fabricated by the Via-First Process1.7.2 TSVs Fabricated by the Via-Middle Process1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process1.7.5 How About the Passive TSV Interposers?1.7.6 Who Wants to Fabricate the TSV for Passive Interposers?1.7.7 Summary and Recommendations1.8 Supply Chains for the TSV Era—Who Does the MEOL, Assembly, and Test?1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers1.8.5 Summary and Recommendations1.9 CMOS Images Sensors with TSVs1.9.1 Toshiba’s DynastronTM1.9.2 STMicroelectronics’ VGA CIS Camera Module1.9.3 Samsung’s S5K4E5YX BSI CIS1.9.4 Toshiba’s HEW4 BSI TCM5103PL1.9.5 Nemotek’s CIS1.9.6 SONY’s ISX014 Stacked Camera Sensor1.10 MEMS with TSVs1.10.1 STMicroelectronics’ MEMS Inertial Sensors1.10.2 Discera’s MEME Resonator1.10.3 Avago’s FBAR MEMS Filter1.11 References2 Through-Silicon Vias Modeling and Testing2.1 Introduction2.2 Electrical Modeling of TSVs2.2.1 Analytic Model and Equations for a Generic TSV Structure2.2.2 Verification of the Proposed TSV Model in Frequency Domain2.2.3 Verification of the Proposed TSV Model in Time Domain2.2.4 TSV Electrical Design Guideline2.2.5 Summary and Recommendations2.3 Thermal Modeling of TSVs2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction2.3.2 Thermal Behavior of a TSV Cell2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations2.3.5 Summary and Recommendations2.4 Mechanical Modeling and Testing of TSVs2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si2.4.2 Experimental Results on Cu Pumping during Manufacturing2.4.3 Cu Pumping under Thermal Shock Cycling2.4.4 Keep-Out-Zone of Cu-Filled TSVs2.4.5 Summary and Recommendations2.5 References3 Stress Sensors for Thin-Wafer Handling and Strength Measurement3.1 Introduction3.2 Design and Fabrication of Piezoresistive Stress Sensors3.2.1 Design of Piezoresistive Stress Sensors3.2.2 Fabrication of the Stress Sensors3.2.3 Summary and Recommendations3.3 Application of Stress Sensors in Thin-Wafer Handling3.3.1 Design, Fabrication, and Calibration of Piezoresistive Stress Sensors3.3.2 Stress Measurement in Wafer after Thinning3.3.3 Summary and Recommendations3.4 Application of Stress Sensors in Wafer Bumping3.4.1 Stresses after UBM Fabrication3.4.2 Stresses after Dry-Film Process3.4.3 Stresses after Solder Bumping Process3.4.4 Summary and Recommendations3.5 Application of Stress Sensors in Drop Test of Embedded Ultrathin Chips3.5.1 Test Vehicle and Fabrication3.5.2 Experimental Setup and Procedure3.5.3 In-Situ Stress Measurement Results3.5.4 Reliability Testing3.5.5 Summary and Recommendations3.6 References4 Package Substrate Technologies4.1 Introduction4.2 Package Substrate with Build-up Layers for Flip Chip 3D IC Integration4.2.1 Surface Laminate Circuit Technology4.2.2 The Trend in Package Substrate with Build-up Layers4.2.3 Summary and Recommendations4.3 Coreless Package Substrates4.3.1 Advantages and Disadvantages of Coreless Package Substrates4.3.2 Substitution of Si Interposer by Coreless Substrates4.3.3 Warpage Problem and Solution of Coreless Substrates4.3.4 Summary and Recommendations4.4 Recent Advance of Package Substrate with Build-up Layer4.4.1 Thin-Film Layers on Top of Build-up Layer of Package Substrate4.4.2 Warpage and Qualification Results4.4.3 Summary and Recommendations4.5 References5 Microbumps: Fabrication, Assembly, and Reliability5.1 Introduction5.2 Fabrication, Assembly, and Reliability of 25-μm-Pitch Microbumps5.2.1 Test Vehicle5.2.2 Structure of the Microbumps5.2.3 Structure of the ENIG Pads5.2.4 Fabrication of the 25-μm-Pitch Microbumps5.2.5 Fabrication of ENIG Bonding Pads on Si Carrier5.2.6 Thermal Compression Bonding Assembly5.2.7 Evaluation of the Underfill5.2.8 Reliability Assessment5.2.9 Summary and Recommendations5.3 Fabrication, Assembly, and Reliability of 20-μm-Pitch Microbumps5.3.1 Test Vehicle5.3.2 Assembly of Test Vehicle5.3.3 Formation of Microjoints by Thermocompression Bonding5.3.4 Microgap Filling5.3.5 Reliability Test5.3.6 Reliability Test Results and Discussion5.3.7 Failure Mechanism of the Microjoints5.3.8 Summary and Recommendations5.4 Fabrication, Assembly, and Reliability of 15-μm-Pitch Microbumps5.4.1 Microbumps and UBM Pads of the Test Vehicle5.4.2 Assembly5.4.3 Assembly with CuSn Solder Microbump and ENIG Pad5.4.4 Assembly with CuSn Solder Microbump and CuSn Solder Microbump5.4.5 Evaluation of Underfill5.4.6 Summary and Recommendations5.5 References6 3D Si Integration6.1 Introduction6.2 The Electronic Industry6.3 Moore’s Law and More-Than-Moore6.4 The Origin of 3D Integration6.5 Overview and Outlook of 3D Si Integration6.5.1 Bonding Methods for 3D Si Integration6.5.2 Cu-to-Cu (W2W) Bonding6.5.3 Cu-to-Cu (W2W) Bonding with Post-Annealing6.5.4 Cu-to-Cu (W2W) Bonding at Room Temperature6.5.5 SiO2-to-SiO2 (W2W) Bonding6.5.6 A Few Notes on W2W Bonding6.6 3D Si Integration Technology Challenges6.7 3D Si Integration EDA Challenges6.8 Summary and Recommendations6.9 References7 2.5D/3D IC Integration7.1 Introduction7.2 TSV Process for 3D IC Integration7.2.1 Tiny Vias on a Chip7.2.2 Via-First Process7.2.3 Via-Middle Process7.2.4 Via-Last from the Front-Side Process7.2.5 Via-Last from the Back-Side Process7.2.6 Summary and Recommendations7.3 The Potential Application of 3D IC Integration7.4 Memory-Chip Stacking7.4.1 The Chips7.4.2 The Potential Products7.4.3 Assembly Process7.5 Wide I/O Memory or Logic-on-Logic7.5.1 The Chips7.5.2 The Potential Products7.5.3 Assembly Process7.6 Wide I/O DRAM or Hybrid Memory Cube7.6.1 The Chips7.6.2 The Potential Products7.6.3 Assembly Process7.7 Wide I/O 2 and High Bandwidth Memory7.8 Wide I/O Interface (2.5D IC Integration)7.8.1 Real Applications of TSV/RDL Passive Interposers7.8.2 Fabrication of Interposers7.8.3 Fabrication of TSVs7.8.4 Fabrication of RDLs7.8.5 Fabrication of RDLs—Polymer/Cu-Plating Method7.8.6 Fabrication of RDLs—Cu Damascene Method7.8.7 A Note on Contact Aligner for Cu Damascene Method7.8.8 Back-Side Processing and Assembly7.8.9 Summary and Recommendations7.9 Thin-Wafer Handling7.9.1 Conventional Thin-Wafer Handling Method7.9.2 TI’s TSV-WCSP Integration Process7.9.3 TSMC’s Thin-Wafer Handling with Polymer7.9.4 TSMC’s Thin-Wafer Handling without Temporary Bonding and De-Bonding7.9.5 Thin-Wafer Handling with a Heat-Spreader Wafer7.9.6 Summary and Recommendations7.10 References8 3D IC Integration with Passive Interposer8.1 Introduction8.2 3D IC Integration with TSV/RDL Interposer8.3 TSV/RDL Interposer with Double-Sided Chip Attachments8.3.1 The Structure8.3.2 Thermal Analysis—Boundary Conditions8.3.3 Thermal Analysis—TSV Equivalent Model8.3.4 Thermal Analysis—Solder Bump/Underfill Equivalent Model8.3.5 Thermal Analysis—Results8.3.6 Thermomechanical Analysis—Boundary Conditions8.3.7 Thermomechanical Analysis—Material Properties8.3.8 Thermomechanical Analysis—Results8.3.9 Fabrication of the TSV8.3.10 Fabrication of the Interposer with Top-Side RDLs8.3.11 TSV Reveal of the Cu-Filled Interposer with Top-Side RDLs8.3.12 Fabrication of the Interposer with Bottom-Side RDLs8.3.13 Passive Electrical Characterization of the Interposer8.3.14 Final Assembly8.3.15 Summary and Recommendations8.4 TSV Interposer with Chips on Both Sides8.4.1 The Structure8.4.2 Thermal Analysis—Material Properties8.4.3 Thermal Analysis—Boundary Conditions8.4.4 Thermal Analysis—Result and Discussions8.4.5 Thermomechanical Analysis—Material Properties8.4.6 Thermomechanical Analysis—Boundary Conditions8.4.7 Thermomechanical Analysis—Results and Discussions8.4.8 Interposer Fabrication8.4.9 Microbump Wafer Bumping8.4.10 Final Assembly8.4.11 Summary and Recommendations8.5 Low-Cost TSH Interposer for 3D IC Integration8.5.1 The New Design8.5.2 Electrical Simulation8.5.3 Test Vehicle8.5.4 Top Chip with UBM/Pad and Cu Pillar8.5.5 Bottom Chip with UBM/Pad/Solder8.5.6 TSH Interposer Fabrication8.5.7 Final Assembly8.5.8 Reliability Assessments8.5.9 Summary and Recommendations8.6 References9 Thermal Management of 2.5D/3D IC Integration9.1 Introduction9.2 Design Philosophy9.3 The New Design9.4 Equivalent Model for Thermal Analysis9.5 Interposer with Chip/Heat Spreader on Its Top Side and Chip on Its Bottom Side9.5.1 The Structure9.5.2 Material Properties9.5.3 Boundary Conditions9.5.4 Simulation Results9.6 Interposer with Chip/Heat Spreader on Its Top Side and Chip/Heat Slug on Its Bottom Side9.6.1 The Structure and Boundary Conditions9.6.2 Simulation Results9.7 Interposer with Four Chips on Its Top Side with Heat Spreader9.7.1 The Structure9.7.2 Boundary Conditions9.7.3 Simulation Results9.7.4 Summary and Recommendations9.8 Thermal Performance between 2.5D and 3D IC Integrations9.8.1 The Structures9.8.2 The Finite Element Models9.8.3 Material Properties and Boundary Conditions9.8.4 Simulation Results—Low-Power Applications9.8.5 Simulation Results—High-Power Applications9.8.6 Summary and Recommendations9.9 Thermal Management System with TSV Interposers with Embedded Microchannels9.9.1 The Structure9.9.2 Adaptor9.9.3 Heat Exchanger9.9.4 Carriers9.9.5 System Integration9.9.6 Theoretical Analysis of the Pressure Drop9.9.7 Experimental Process9.9.8 Results and Discussions9.9.9 Summary and Recommendations9.10 References10 Embedded 3D Hybrid Integration10.1 Introduction10.2 Trends of Optoelectronic Products10.3 The Old Design—High-Frequency Data Link on PCB Using Optical Waveguides10.3.1 Polymer Optical Waveguide10.3.2 Simulations—Optical Coupling Models10.3.3 Simulations—System Link Design10.3.4 Assembly of the OECB10.3.5 Measurement Results of the OECB10.3.6 Summary and Recommendations10.4 The Old Design—Embedded Board-Level Optical Interconnects10.4.1 Fabrication of Polymer Waveguide10.4.2 Fabrication of the 45° Micro-Mirror10.4.3 Assembly Process of the OECB10.4.4 Fabrication Process of Vertical-Optical Channel10.4.5 Final Assembly10.4.6 Summary and Recommendations10.5 The New Designs10.6 An Embedded 3D Hybrid Integration Design Example10.6.1 Optical Design, Analysis, and Results10.6.2 Thermal Design, Analysis, and Results10.6.3 Mechanical Design, Analysis, and Results10.6.4 Summary and Recommendations10.7 Semi-Embedded TSV Interposer with Stress Relief Gap10.7.1 Design Philosophy10.7.2 Problem Definition10.7.3 Semi-Embedded TSV Interposer Subjected to Operating Condition10.7.4 Semi-Embedded TSV Interposer Subjected to an Environmental Condition10.7.5 Summary and Recommendations10.8 References11 3D LED and IC Integration11.1 Introduction11.2 Status and Outlook of Haitz’s Law11.3 LED Has Come a Long Way!11.4 Four Key Segments of LED Products11.4.1 Substrates for LED Epitaxial Deposition11.4.2 LED Device Fabrication11.4.3 Packaging Assembly and Test of LED11.4.4 LED Final Product Assembly11.4.5 Outlook of LED Products11.5 3D LED and IC Integration11.5.1 HP FCLED and Thin-Film FCLED11.5.2 3D LED and IC Integration Packages11.5.3 Manufacturing Process of 3D LED and IC Integration11.5.4 Summary and Recommendations11.6 2.5D IC and LED Integration11.6.1 LED Packaging Using Si-Substrate with Cavities and Cu-Filled TSVs11.6.2 Si-Substrate with Cavity and TSVs for LED Packaging11.6.3 LED Wafer-Level Packaging11.6.4 Summary and Recommendation11.7 Thermal Management of 3D LED and IC Integration11.7.1 The New Designs11.7.2 3D IC and LED Integration: A Design Example11.7.3 Boundary-Value Problem11.7.4 Simulation Results (Channel Height = 700 μm)11.7.5 Simulation Results (Channel Height = 350 μm)11.7.6 Summary and Recommendations11.8 References12 3D MEMS and IC Integration12.1 Introduction12.2 MEMS Packaging12.3 Design of 3D MEMS and IC Integration12.3.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through12.3.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC12.3.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in the Package Cap12.3.4 3D MEMS and IC Integration with MEMS on ASIC with TSVs12.3.5 2.5D/2.25D MEMS and IC Integration12.4 Assembly Process of 3D MEMS and IC Integration12.4.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through12.4.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC12.4.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in Package Cap12.4.4 A Note on Case 10—A Real 3D MEMS and IC Integration12.4.5 Summary and Recommendations12.5 Low-Temperature Bonding of 3D MEMS Packaging with Solders12.5.1 3D IC and MEMS Integration with Different Chip Sizes12.5.2 Cavity and TSVs in Cap Wafer12.5.3 MEMS Chip to ASIC Wafer (C2W) Bonding12.5.4 ASIC Wafer with MEMS Chips to Cap Wafer (W2W) Bonding12.5.5 Summary and Recommendations12.6 Recent Developments in Advanced MEMS Packaging12.6.1 TSVs for Wafer-Level Packaging of RF MEMS Devices12.6.2 Zero-Level Packaging for RF-MEMS Implementing TSVs and Metal Bonding12.6.3 MEMS Package Based on Si-Interposer Wafer with Cu-Filled TSVs12.6.4 Wafer-Scale Packaging for FBAR-Based Oscillators12.6.5 Summary and Recommendations12.7 References13 3D CMOS Image Sensor and IC Integration13.1 Introduction13.2 FI-CIS and BI-CIS13.3 3D CIS and IC Stacking13.3.1 The Structure13.3.2 Fabrication of the CIS Pixel Wafer and Logic IC Wafer13.4 3D CIS and IC Integration13.4.1 The Structure13.4.2 Fabrication Process Flow of the Coprocessor Wafer13.4.3 Fabrication Process Flow of the CIS Wafer13.4.4 Final Assembly13.5 Summary and Recommendations13.6 References14 3D IC Packaging14.1 Introduction14.2 Chip Stacking by Wirebonding14.2.1 Au Wire14.2.2 Cu Wire and Ag Wire14.3 Package-on-Package (PoP)14.3.1 Wirebonding PoP14.3.2 Flip Chip PoP14.3.3 Wirebonding Package on Flip Chip Package14.3.4 PoP in iPhone 5s14.4 Wafer-Level Packaging14.4.1 Fan-In WLP14.4.2 3D Chip-to-Chip WLP14.5 Fan-Out eWLP14.5.1 Fan-Out eWLP14.5.2 3D eWLP—Two-Chip Stacking14.5.3 3D eWLP—Chip on eWLP (Face-to-Face)14.5.4 3D eWLP—Chip on eWLP (Face-to-Back)14.5.5 3D eWLP—Package on eWLP14.5.6 3D eWLP—eWLP on eWLP14.6 Embedded Panel-Level Packaging14.6.1 Advantages and Disadvantages14.6.2 Various Chip-Embedding Processes14.6.3 Embedded Chip in SiP Rigid Substrate14.6.4 3D Embedded Chip in SiP Flexible Substrate14.6.5 3D Embedded Stacking Chips in SiP Flexible Substrate14.7 Summary and Recommendations14.8 ReferencesIndex