VLSI-SoC: Research Trends in VLSI and Systems on Chip

Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France

Häftad, Engelska, 2010

Av Giovanni De Micheli, Salvador Mir, Ricardo Reis

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This book contains extended and revised versions of the best papers that were presented during the fourteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference.

Produktinformation

Utgivningsdatum2010-11-23
Mått155 x 235 x 23 mm
Vikt616 g
FormatHäftad
SpråkEngelska
SerieIFIP Advances in Information and Communication Technology
Antal sidor394
FörlagSpringer-Verlag New York Inc.
ISBN9781441945174

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Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.- Oversampled Time Estimation Techniques for Precision Photonic Detectors.- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.- Electronic Detection of DNA Adsorption and Hybridization.- Probabilistic amp; Statistical Design—the Wave of the Future.- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.- Soft Error Resilient System Design through Error Correction.- Library Compatible Variational Delay Computation.- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots.- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.- Logic Synthesis of EXOR Projected Sum of Products.- A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.- CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.- Designing Routing and Message-Dependent Deadlock Free Networks on Chips.- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.- Human++: Emerging Technology for Body Area Networks.