The Designer's Guide to VHDL

Inbunden, Engelska, 2008

969 kr

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VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard
Helps readers get up to speed quickly with new features of the new standard
Presents a structured guide to the modeling facilities offered by VHDL
Shows how VHDL functions to help design digital systems
Includes extensive case studies and source code used to develop testbenches and case study examples
Helps readers gain maximum facility with VHDL for design of digital systems

Produktinformation

Utgivningsdatum2008-07-01
Mått196 x 243 x 50 mm
Vikt1 780 g
FormatInbunden
SpråkEngelska
SerieSystems on Silicon
Antal sidor936
Upplaga3
FörlagElsevier Science
ISBN9780120887859

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Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

1. Fundamental Concepts2. Scalar Data Types and Operations3. Sequential Statements4. Composite Data Types and Operations5. Basic Modeling Constructs6. Case Study: A Pipelined Complex Multiplier Accumulator7. Subprograms8. Packages and Use Clauses9. Aliases10. External Names in Testbenches11. Properties and Assertion-Based Design12. Resolved Signals13. Generics14. Components and Configurations15. Generate Statements16. Access Types and Abstract Data Types17. Files and Input/Output18. Case Study: Queuing Networks19. Attributes and Groups20. Design for Synthesis21. Case Study: System Design using the Gumnut Core22. Miscellaneous TopicsAppendixA. Standard PackagesB. Related StandardsC. VHDL SyntaxD. Differences Among VHDL VersionsE. Answers to Exercises