Scalable Hardware Verification with Symbolic Simulation

The book overviews current formal verification methods and provides an in-depth analysis of some advanced techniques to improve the scalability of these methods and to close the gap between design and verification in computer-aided design. It provides the theoretical background required to present such methods and advanced techniques, i.e. Boolean function representations, models of sequential networks and, in particular, some novel algorithms to expose the disjoint support decompositions of Boolean functions, used in one of the scalable approaches.