RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design 1
bokomslag RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Vetenskap & teknik

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Stuart Sutherland

Häftad

2039:-

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  • 488 sidor
  • 2017
  • Författare: Stuart Sutherland
  • Format: Häftad
  • ISBN: 9781546776345
  • Språk: Engelska
  • Antal sidor: 488
  • Utgivningsdatum: 2017-06-01
  • Förlag: Createspace Independent Publishing Platform

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