Resource Efficient LDPC Decoders

From Algorithms to Hardware Architectures

Häftad, Engelska, 2017

AvVikram Arkalgud Chandrasetty,Syed Mahfuzul Aziz

1 669 kr

Beställningsvara. Skickas inom 10-15 vardagar. Fri frakt för medlemmar vid köp för minst 249 kr.

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.
The reader will learn:

Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
How to reduce computational complexity and power consumption using computer aided design techniques
All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

Provides extensive treatment of LDPC decoding algorithms and hardware implementations
Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

Produktinformation

Utgivningsdatum2017-12-05
Mått191 x 235 x 10 mm
Vikt390 g
FormatHäftad
SpråkEngelska
Antal sidor190
FörlagElsevier Science
ISBN9780128112557

Tillhör följande kategorier

Elektronik och kommunikationer inom Naturvetenskap och teknik

Vikram Chandrasetty received Bachelor Degree in Electronics and Communication Engineering from Bangalore University (INDIA), Master Degree in VLSI System Design from Coventry University (UK) and PhD in Computer Systems Engineering from the University of South Australia (Australia). During his post-doctoral research fellowship at the University of New Castle (Australia) he worked on designing spatially coupled LDPC codes and hardware implementations. He reviews articles for many journals including Elsevier and IEEE Transactions. Vikram also has substantial experience as a professional engineer. He has worked on ASIC/FPGA design, error correction coding, electronic design automation, cryptography and communication systems for renowned companies including Motorola and SanDisk. He is currently working on designing memory controllers for next generation storage products in Western Digital. Syed Mahfuzul Aziz is a professor of Electrical and Electronic Engineering at the University of South Australia. His research interests are in the areas of digital systems, integrated circuit design, wireless sensor networks and smart energy systems. He leads research teams working in low power embedded processing architectures, reconfigurable sensing platforms, integration of novel sensors with electronics and communications. Prof Aziz has extensive experience in technology applications through collaborative projects and has led many industry funded projects. His recent industry collaborations involve emerging IoT applications in organic waste management, water and agriculture sectors. As lead investigator, he has attracted competitive funding from Australian Research Council and Australian government agencies, and also funding from various industry sectors including defence and health. Professor Aziz is a senior member of the IEEE. He was the recipient of the Prime Minister’s Award for Australian University Teacher of the year in 2009.

1. Introduction2. Overview of LDPC codes3. Structure and flexibility of LDPC codes4. LDPC decoding algorithms5. LDPC decoder architectures6. Hardware implementation of LDPC decoder7. LDPC decoders in multimedia communication8. Prospective LDPC applicationsAppendixA : Sample C-Programs and MATLAB models for LDPC code construction and simulationB : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture