Post-Silicon Validation and Debug

Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include embedded and cyber-physical systems, energy-aware computing, hardware security and trust, system-on-chip verification, bioinformatics, and post-silicon validation and debug. He received his Ph.D. in Computer Science and Engineering from the University of California, Irvine. He has published six books and more than 150 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three best paper awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as the Deputy Editor-in-Chief of IET Computers & Digital Techniques, and as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. Currently, he is serving as the Program Chair of International Conference on VLSI Design and International Conference on Embedded Systems. He has served on many conference organizing committees and technical program committees of premier ACM and IEEE conferences. He is currently serving as an ACM Distinguished Speaker. Prof. Mishra is an ACM Distinguished Scientist and a Senior Member of IEEE. Farimah Farahmandi received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran in 2010 and 2013, respectively. Her research is focused on developing analytical models and computational methods for design and verification of secure, trustworthy and energy-efficient systems. During her Ph.D., she has actively collaborated with various research groups (IBM, NXP, Intel, and Cisco) that have led to several joint publications. Her research has resulted in one book, six book chapters, and thirteen publications in premier ACM/IEEE journals and conferences. Her research has been recognized by several awards including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, nomination for Best Paper Award in ASPDAC 2017, DAC Richard Newton Young Student Fellowship, and SIGDA Ph.D. Forum at DAC. She was a research intern in advanced security research group at Cisco in summer 2016.

• Part 1. Introduction.- Post-Silicon SoC Validation Challenges.- Part 2. Debug Infrastructure.- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness.- Structure-based Signal Selection for Post-silicon Validation.- Simulation-based Signal Selection.- Hybrid Signal Selection.- Post-Silicon Signal Selection using Machine Learning.- Part 3. Generation of Tests and Assertions.- Observability-aware Post-Silicon Test Generation.- On-chip Constrained-Random Stimuli Generation.- Test Generation and Lightweight Checking for Multi-core Memory Consistency.- Selection of Post-Silicon Hardware Assertions.- Part 4. Post-Silicon Debug.- Debug Data Reduction Techniques.- High-level Debugging of Post-silicon Failures.- Post-silicon Fault Localization with Satisfiability Solvers.- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes.- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis.- Part 5. Case Studies.- Network-on-Chip Validation and Debug.- Post-silicon Validation of the IBM Power8 Processor.- Part 6. Conclusion and Future Directions.- SoC Security versus Post-Silicon Debug Conflict.- The Future of Post-Silicon Debug.