Oversampled Delta-Sigma Modulators

The analysis of the quantization noise in delta-sigma modulators is not a trivial task. State-of-the-art analysis methods include modelling the quantization noise as a uniform distributed white noise. However, it is not uncommon to observe limit cycle oscillations and tones at the output of a delta-sigma modulator. In most of the applications, these limit cycles and tones are strictly objectionable. Such an application, for instance, is a Fractional-N PLL frequency synthesizer, where idle tones and limit cycles generated from the delta-sigma modulator directly appear in the synthesized RF waveform as spurious components. The relatively small conversion bandwidth is another important limitation of delta-sigma modulators. Due to their oversampling nature, delta-sigma modulators have been used in low frequency applications. This book presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures.It has been proved that appropriately set initial conditions generate tone-free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order and the book contains sufficient detail to enable readers with little background in the subject to easily follow the material in it. It should be of interest to graduate students, researchers and practising circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design.