Nanoscale CMOS

Francis Balestra is Director of the Laboratoire de Physique des Composants - Semiconducteurs (LPCS) at INP Grenoble in France. He has coauthored over 80 publications in international scientific journals and 120 communications at national and international conferences (20 invited papers and review articles).

• Introduction xvF. BALESTRAPART 1. NOVEL MATERIALS FOR NANOSCALE CMOS 1Chapter 1. Introduction to Part 1 3D. LEADLEY, A. DOBBIE, V. SHAH and J. PARSONS1.1. Nanoscale CMOS requirements 31.2. The gate stack – high-_ dielectrics 51.3. Strained channels 71.4. Source-drain contacts 161.5. Bibliography 17Chapter 2. Gate Stacks 23O. ENGSTRÖM, I. Z. MITROVIC, S. HALL, P. K. HURLEY, K. CHERKAOUI, S. MONAGHAN, H. D. B. GOTTLOB and M. C. LEMME2.1. Gate-channel coupling in MOSFETs 232.2. Properties of dielectrics 242.3. Interfaces states and bulk oxide traps 292.4. Two ternary compounds: GdSiO and LaSiO 392.5. Metal gate technology 502.6. Future outlook 562.7. Bibliography 58Chapter 3. Strained Si and Ge Channels 69D. LEADLEY, A. DOBBIE, M. MYRONOV, V. SHAH and E. PARKER3.1. Introduction 693.2. Relaxation of strained layers 743.3. High Ge composition Si1–xGex buffers  833.4. Ge channel devices 1053.5. Acknowledgements 1153.6. Bibliography 115Chapter 4. From Thin Si/SiGe Buffers to SSOI 127S. MANTL and D. BUCA4.1. Introduction 1284.2. Nucleation of dislocations 1294.3. Strain relaxation and strain transfer mechanisms 1314.4. Overgrowth of strained Si and layer optimization 1344.5. Characterization of the elastic strain 1374.6. SSOI wafer fabrication 1414.7. SSOI as channel material for MOSFET devices 1454.8. Summary 1524.9. Bibliography 153Chapter 5. Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration 157E. DUBOIS, G. LARRIEU, R VALENTIN, N. BREIL and F. DANNEVILLE5.1. Introduction 1575.2. Challenges associated with the source/drain extrinsic contacts 1585.3. Extraction of low Schottky barriers 1665.4. Modulation of Schottky barrier height using low temperature dopant segregation 1775.5. State-of-the-art device integration 1915.6. Conclusion 1955.7. Acknowledgements 1975.8. Bibliography 197PART 2. ADVANCED MODELING AND SIMULATION FOR NANO-MOSFETS AND BEYOND-CMOS DEVICES 205Chapter 6. Introduction to Part 2 207E. SANGIORGI6.1. Modeling and simulation approaches for gate current computation 2086.2. Modeling and simulation approaches for drain current computation 2096.3. Modeling of end of the roadmap nMOSFET with alternative channel material 2096.4. NEGF simulations of nanoscale CMOS in the effective mass approximation 2106.5. Compact models for advanced CMOS devices 2116.6. Beyond CMOS 2116.7. Bibliography 212Chapter 7. Modeling and Simulation Approaches for Gate Current Computation 213B. MAJKUSIAK, P. PALESTRI, A. SCHENK, A. S. SPINELLI, C. M. COMPAGNONI and M. LUISIER7.1. Introduction 2137.2. Calculation of the tunneling probability 2167.3. Tunneling in nonconventional devices 2287.4. Trap-assisted tunneling 2377.5. Models for gate current computation in commercial TCAD 2437.6. Comparison between modeling approaches 2497.7. Bibliography 251Chapter 8. Modeling and Simulation Approaches for Drain Current Computation 259M. VASICEK, D. ESSENI, C. FIEGNA and T. GRASSER8.1. Boltzmann transport equation for MOS transistors 2608.2. Method of moments 2628.3. Subband macroscopic transport models 2768.4. Comparison with device-SMC 2788.5. Conclusions 2828.6. Bibliography 283Chapter 9. Modeling of End of the Roadmap nMOSFET with Alternative Channel Material 287Q. RAFHAY, R. CLERC, G. GHIBAUDO, P. PALESTRI and L. SELMI9.1. Introduction: replacing silicon as channel material 2879.2. State-of-the-art in the modeling of alternative channel material devices 2909.3. Critical analysis of the literature using analytical models 2979.4. Conclusions 3279.5. Bibliography 328Chapter 10. NEGF for 3D Device Simulation of Nanometric Inhomogenities 335A. MARTINEZ, A. ASENOV and M. PALA10.1. Introduction 33510.2. Variabilities for nanoscale CMOS 34310.3. Full quantum treatment of spatial fluctuations in ultra-scaled devices 36110.4. Bibliography 377Chapter 11. Compact Models for Advanced CMOS Devices 381B. IÑIGUEZ, F. LIME, A. LÁZARO and T. A. FJELDLY11.1. Introduction 38111.2. Electrostatics modeling issues 38511.3. Transport modeling issues 38811.4. 1D compact models 39011.5. Ultimate MuGFET modeling issues: ballistic current and quantum confinement 40511.6. Velocity saturation and channel length modulation modeling 40911.7. Hydrodynamic transport model 41111.8. Charge and capacitance modeling 41311.9. Short-channel effects 42011.10. RF and noise modeling 43411.11. Acknowledgements 43711.12. Bibliography 438Chapter 12. Beyond CMOS 443G. IANNACCONE, G. FIORI, S. REGGIANI and M. PALA12.1. Introduction 44312.2. Atomistic modeling of carbon-based FETs 44412.3. Numerical simulation of CNT-FETs 44712.4. Effective mass modeling of carbon nanotube FETs 45112.5. CNT versus graphene nanoribbon FETs 45912.6. Full-quantum treatment of elastic and inelastic scattering in Si and SiC GAA nanowire FETs 46112.7. Conclusions 46712.8. Bibliography 468PART 3. NANOCHARACTERIZATION METHODS 471Chapter 13. Introduction to Part 3 473D. FLANDREChapter 14. Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors 475M. MOUIS and G. GHIBAUDO14.1. Impact of transport on device performance in the drift-diffusion regime 47614.2. Standard extraction techniques and their adaptation to short channel transistors 48214.3. Alternative extraction techniques 51814.4. Out of equilibrium transport 53114.5. Conclusions 53714.6. Bibliography 539Chapter 15. Characterization of Interface Defects 545P. HURLEY, O. ENGSTRÖM, D. BAUZA and G. GHIBAUDO15.1. Characterization using the capacitance-voltage (C-V) response 54515.2. Characterization using the conductance-voltage (G-V) response 55015.3. Charge pumping 55315.4. Low frequency noise 56115.5. Bibliography 566Chapter 16. Strain Determination 575A. O’NEILL, S. OLSEN, P. DOBROSZ, R. AGAIBY and Y. TSANG16.1. Introduction 57516.2. Characterization requirements 57516.3. Characterization techniques 57916.4. Strain description 59216.5. Bibliography 598Chapter 17. Wide Frequency Band Characterization 603D. FLANDRE, J.-P. RASKIN and V. KILCHYTSKA17.1. Modified split-CV technique for reliable mobility extraction 60417.2. Small-signal electrical characterization of FinFETs: impact of access resistances and capacitances 61017.3. Substrate-related output conductance degradation 61917.4. Small-signal electrical characterization of Schottky barrier MOSFETs 62617.5. Bibliography 632List of Authors 639Index 649

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