MOS Devices for Low-Voltage and Low-Energy Applications

Yasuhisa Omura, Professor, Department of Electrical and Electronic Engineering, Kansai University, Osaka, Japan. Professor Omura received his Ph.D. degree in Engineering from Kyushu University, Japan, in 1984. For the past three decades, he has engaged in the research of devices physics analysis and modeling of SOI MOSFET and Lubistor. Professor Omura published more than 300 papers and he is the editor/co-editor of five books. He has been an IEEE Fellow since 2010.Abhijit Mallik, Professor, Department of Electronic Science, University of Calcutta, IndiaNaoto Matsuo, Associate Professor, Department of Electrical and Electronic Engineering, Yamaguchi University, Japan

• Preface xvAcknowledgments xviPart I INTRODUCTION TO LOW‐VOLTAGE AND LOW‐ENERGY DEVICES 11 Why Are Low‐Voltage and Low‐Energy Devices Desired? 3References 42 History of Low‐Voltage and Low‐Power Devices 52.1 Scaling Scheme and Low‐Voltage Requests 52.2 Silicon‐on‐Insulator Devices and Real History 8References 103 Performance Prospects of Subthreshold Logic Circuits 123.1 Introduction 123.2 Subthreshold Logic and its Issues 123.3 Is Subthreshold Logic the Best Solution? 13References 13Part II SUMMARY OF PHYSICS OF MODERN SEMICONDUCTOR DEVICES 154 Overview 17References 185 Bulk MOSFET 195.1 Theoretical Basis of Bulk MOSFET Operation 195.2 Subthreshold Characteristics: “OFF State” 195.2.1 Fundamental Theory 195.2.2 Influence of BTBT Current 235.2.3 Points to Be Remarked 245.3 Post‐Threshold Characteristics: “ON State” 245.3.1 Fundamental Theory 245.3.2 Self‐Heating Effects 265.3.3 Parasitic Bipolar Effects 275.4 Comprehensive Summary of Short‐Channel Effects 27References 286 SOI MOSFET 296.1 Partially Depleted Silicon‐on‐Insulator Metal Oxide Semiconductor Field‐Effect Transistors 296.2 Fully Depleted (FD) SOI MOSFET 306.2.1 Subthreshold Characteristics 306.2.2 Post‐Threshold Characteristics 366.2.3 Comprehensive Summary of Short‐Channel Effects 416.3 Accumulation‐Mode (AM) SOI MOSFET 416.3.1 Aspects of Device Structure 416.3.2 Subthreshold Characteristics 426.3.3 Drain Current Component (I) – Body Current (ID,body) 436.3.4 Drain Current Component (II) – Surface AccumulationLayer Current (ID,acc) 456.3.5 Optional Discussions on the Accumulation Mode SOI MOSFET 456.4 FinFET and Triple‐Gate FET 466.4.1 Introduction 466.4.2 Device Structures and Simulations 466.4.3 Results and Discussion 476.4.4 Summary 496.5 Gate‐all‐Around MOSFET 50References 517 Tunnel Field‐Effect Transistors (TFETs) 537.1 Overview 537.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 537.2.1 Introduction 537.2.2 Device Modeling 547.2.3 Numerical Calculation Results and Discussion 617.2.4 Summary 657.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 657.3.1 Introduction 657.3.2 Device Structure and Model Concept 657.3.3 Comparing Model Results with TCAD Results 697.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 727.3.5 Summary 757.4 Appendix Integration of Eqs. (7.14)–(7.16) 76References 78Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 818 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 838.1 Introduction 838.2 Subthreshold Operation and Device Simulation 848.3 Model Description 858.4 Results 868.5 Summary 90References 909 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 919.1 Introduction 919.2 Device Structures and Simulation 929.3 Subthreshold Operation 939.4 Device Optimization for Subthreshold Analog Operation 959.5 Subthreshold Analog Circuit Performance 989.6 CMOS Amplifiers with Large Geometry Devices 1059.7 Summary 106References 10710 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 10810.1 Introduction 10810.2 Circuit Description 10810.3 Device Structure and Simulation 11010.4 Results and Discussion 11010.5 PTAT as a Temperature Sensor 11610.6 Summary 116References 11611 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 11711.1 Introduction 11711.2 Device Structure and Simulation 11811.3 Results and Discussion 12011.4 Summary 126References 12712 Performance Prospect of Low‐Power Bulk MOSFETs 128Reference 129Part IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 13113 Demand for High‐Performance SOI Devices 13314 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 13414.1 Introduction 13414.2 Device Design Concept for 100 nm Gate SOI CMOS 13414.3 Device Fabrication 13614.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 13714.4.1 Threshold and Subthreshold Characteristics 13714.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET/SIMOX 13814.4.3 ID–VD and ID–VG Characteristics of 85‐nm‐Gate MOSFET/SIMOX 14214.4.4 Switching Performance 14214.5 Discussion 14214.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 14214.6 Summary 144References 14515 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 14715.1 Introduction 14715.2 Device Structure and Simulations 14815.3 Proposed Model for Minimum Channel Length 14915.3.1 Minimum Channel Length Model Constructed using Extract A 14915.3.2 Minimum Channel Length Model Constructed using Extract B 15015.4 Performance Prospects of Scaled SOI MOSFETs 15215.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 15215.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 15715.5 Summary 162References 16216 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 16416.1 Introduction 16416.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 16516.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 17216.4 Summary 17616.5 Appendix: A Simulation Model for Minority Carrier Lifetime 17716.6 Appendix: Design Guideline for SOI‐QDs 177References 17817 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 18017.1 Introduction 18017.2 Simulations 18117.3 Results and Discussion 18317.3.1 DC Characteristics and Switching Performance: Device A 18317.3.2 RF Analog Characteristics: Device A 18417.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 18517.3.4 Impact of Simulation Model on Simulation Results 18917.4 Summary 192References 19218 Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 19418.1 Introduction 19418.2 Device Structures and Simulation Model 19518.3 Results and Discussion 19618.3.1 Impact of S/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 19618.3.2 Tradeoff of Short‐Channel Effects and Drivability 19618.4 Summary 201References 20119 Gate Field Engineering and Source/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 20319.1 Introduction 20319.2 Device Structures Assumed and Physical Parameters 20419.3 Simulation Results and Discussion 20619.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 20619.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 21219.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 21619.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 21719.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 21819.3.6 Proposal for Possible GAA Wire MOSFET Structure 22019.4 Summary 22119.5 Appendix: Brief Description of Physical Models in Simulations 221References 22520 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 22820.1 Introduction 22820.2 Device Structure and Simulations 22920.3 Results and Discussion 23020.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 23020.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 23520.3.3 Behaviors of Drivability and Off‐Current 23720.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 23920.4 Summary 239References 240Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 24121 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET/SIMOX 24321.1 Introduction 24321.2 Device Fabrication 24421.3 Device Characteristics 24521.4 Performance of CMOS Amplifier 24721.5 Summary 249References 24922 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 25022.1 Introduction 25022.2 Device Structure and Assumptions for Modeling 25122.2.1 Device Structure and Features of XCT Device 25122.2.2 Basic Assumptions for Device Modeling 25322.2.3 Derivation of Model Equations 25422.3 Results and Discussion 25822.3.1 Measured Characteristics of XCT Devices 25822.4 Design Guidelines 26122.4.1 Drivability Control 26122.4.2 Scaling Issues 26222.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 26522.5 Summary 26722.6 Appendix: Calculation of MOSFET Channel Current 26722.7 Appendix: Basic Condition for Drivability Control 271References 27123 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 27423.1 Introduction 27423.2 Device Structure and Assumptions for Simulations 27423.2.1 Device Structure and Features 27423.2.2 Assumptions for Simulations 27723.3 Proposal for Voltage Reference Circuits and Simulation Results 27823.3.1 Two‐Reference Voltage Circuit 27823.3.2 Three‐Reference Voltage Circuit 28323.4 Summary 283References 28424 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 28524.1 Introduction 28524.2 Device Structure and Assumptions for Modeling 28624.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 28824.4 Further Scaling Potential of XCT‐SOI MOSFET 29124.5 Performance Expected from the Scaled XCT‐SOI MOSFET 29224.6 Summary 296References 296Part VI QUANTUM EFFECTS AND APPLICATIONS – 1 29725 Overview 299References 29926 Si Resonant Tunneling MOS Transistor 30126.1 Introduction 30126.2 Configuration of SRTMOST 30226.2.1 Structure and Electrostatic Potential 30226.2.2 Operation Principle and Subthreshold Characteristics 30426.3 Device Performance of SRTMOST 30726.3.1 Transistor Characteristics of SRTMOST 30726.3.2 Logic Circuit Using SRTMOST 31026.4 Summary 312References 31227 Tunneling Dielectric Thin‐Film Transistor 31427.1 Introduction 31427.2 Fundamental Device Structure 31527.3 Experiment 31527.3.1 Experimental Method 31527.3.2 Calculation Method 31727.4 Results and Discussion 32027.4.1 Evaluation of SiNx Film 32027.4.2 Characteristics of the TDTFT 32027.4.3 TFT Performance at Low Temperatures 32427.4.4 TFT Performance at High Temperatures 32427.4.5 Suppression of the Hump Effect by the TDTFT 33027.5 Summary 336References 33628 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 33928.1 Introduction 33928.2 Device Structure and Model 33928.3 Calculation Results 34028.4 Summary 343References 34329 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 34429.1 Introduction 34429.2 Simulation Model 34529.3 Simulation Results and Discussion 34929.3.1 Fundamental Properties of TBJ MOSFET 34929.3.2 Optimization of Device Parameters and Materials 34929.4 Summary 357References 35730 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 35830.1 Introduction 35830.2 Device Structure and Device Model for Simulations 35930.3 Simulation Results and Discussion 36030.3.1 Current Drivability 36130.3.2 Threshold Voltage Issue 36230.3.3 Subthreshold Characteristics 36330.3.4 Radio‐Frequency Characteristics 36330.4 Summary 365References 36531 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 36731.1 Introduction 36731.2 Device Structure and Simulations 36831.3 Results and Discussion 37131.3.1 Room‐Temperature Characteristics 37131.3.2 High‐Temperature Characteristics 37331.4 Summary 377References 379Part VII QUANTUM EFFECTS AND APPLICATIONS – 2 38132 Overview of Tunnel Field‐Effect Transistor 383References 38533 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 38633.1 Introduction 38633.2 Device Structure and Simulation 38733.3 Results and Discussion 38733.3.1 Effects of Variation in the Spacer Dielectric Constant 38733.3.2 Effects of Variation in the Spacer Width 39133.3.3 Effects of Variation in the Source Doping Concentration 39233.3.4 Effects of a Gate‐Source Overlap 39433.3.5 Effects of a Gate‐Channel Underlap 39433.4 Summary 397References 39734 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 39934.1 Introduction 39934.2 Device Structure and Simulation 39934.3 Results and Discussion 40034.3.1 Effects of Variation in the Gate Dielectric Constant 40034.3.2 Effects of Variation in the Spacer Dielectric Constant 40834.4 Summary 410References 41035 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 41235.1 Introduction 41235.2 Device Structure and Process Steps 41335.3 Simulation Setup 41435.4 Results and Discussion 41635.4.1 Impact of Variation in the Spacer‐Drain Overlap 41635.4.2 Influence of Drain on the Device Characteristics 42435.4.3 Impact of Scaling 42635.5 Summary 429References 43036 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 43136.1 Introduction 43136.2 Proposed Device Structure 43136.3 Simulation Setup 43236.4 Results and Discussion 43436.4.1 Device Characteristics 43436.4.2 Effects of Different Structural Parameters 43536.4.3 Optimization of Different Structural Parameters 43636.5 Summary 445References 445Part VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 44737 Performance Comparison of Modern Devices 449References 45038 Emerging Device Technology and the Future of MOSFET 45238.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 45238.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453References 45439 How Devices Are and Should Be Applied to Circuits 45639.1 Past Approach 45639.2 Latest Studies 456References 45740 Prospects for Low‐Energy Device Technology and Applications 458References 459Bibliography 460Index 463