Logic Synthesis for Multi-Core Counter-Based Control Units

Alexander Barkalov is a member of HiPEAC and Professor of Computer Engineering at the University of Zielona Góra, Poland, and Donetsk National Technical University, Ukraine. He holds an M.Sc. in Computer Engineering, a Ph.D. in Computer Science, and a Doctor of Technical Sciences degree. His research focuses on digital automata theory, particularly the synthesis and optimization of control units using field-programmable logic devices. Dr. Barkalov has also contributed to the development of computer-aided design tools for control units.Larysa Titarenko is a HiPEAC member and Professor of Telecommunications at the University of Zielona Góra, Poland, and Kharkov National University of Radioelectronics, Ukraine. She holds M.Sc., Ph.D., and Doctor of Technical Sciences degrees in Telecommunications. Her research interests include telecommunication systems, antenna theory, and digital automata applications. Dr. Titarenko has been actively involved in research projects sponsored by the Ministry of Science and Higher Education of Ukraine.Kamil Mielcarek is an Assistant Professor at the University of Zielona Góra, Poland, specializing in computer engineering. He holds an M.Sc. in Computer Engineering and a Ph.D. in Computer Science. His research focuses on logic synthesis, FPGA-based control units, VLSI-based FSMs, and network system safety. Dr. Mielcarek has expertise in hardware description languages and algorithmic theory.Małgorzata Mazurkiewicz is an Assistant Professor at the University of Zielona Góra, Poland. She holds an M.Sc. and Ph.D. in Computer Science, with research interests in digital circuit synthesis, design, and PLC programming. Dr. Mazurkiewicz has contributed to advancing methodologies in digital circuit design and automation.

• 1 Sequential Devices and Field-Programmable Gate Arrays 2 Structural Decomposition in Logic Design 3 Single-Core Optimization of CMCU 4 Multi-Core Implementation of Finite State Mashines 5 Multi-Core Implementing C-FSMs with Twofold State Assignment 6 Multi-Core Implementing C-FSMs with Composite State Assignment Conclusion