The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. A reference work for graduate students, senior undergraduates and researchers.