Interconnections for Computer Communications and Packet Networks

Roberto Rojas-Cessa received a B.S. Degree in Electronic Instrumentation from Universidad Veracruzana, Mexico; a M.Sc. in Electrical Engineering from Center for Research and Advanced Studies and Research of the National Polytechnic Institute, Mexico; a M.Sc. degree in Computer Engineering; and a Ph.D. degree in Electrical Engineering from NYU Tandon School of Engineering, Brooklyn, NY. Currently, Dr. Rojas-Cessa is an Associate Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology. He has been involved in the design and implementation of application specific integrated circuits (ASIC) for biomedical applications and high-speed computer communications, as well as the development of high-performance and large capacity packet switches. He was part of the team designing a 40 Tb/s core router in Coree, Inc, in Tinton Falls, NJ. His research interests include high-speed switching and routing, fault tolerance, quality-of-service networks, network measurements, and distributed systems. He is a co-author of the book "Advanced Internet Protocols, Services, and Applications," Wiley and Sons, 2012. Dr. Rojas-Cessa was a Visiting Professor in Thammasat University, Thailand. His research has been funded by U.S. National Science Foundation, Japan Society for the Promotion of Science, and other institutions. Dr. Rojas-Cessa is involved in several technical and organizing committees of IEEE conferences, serves as a reviewer for a large number of technical journals, and is a member of the editorial board of the journals Conference Papers in Science and Elektronica. He has served as a reviewer and panelist for U.S. National Science Foundation and U.S. Department of Energy. He is the author of over 100 conference and journal papers and an inventor of 10 U.S. patents, with a similar number of patent applications pending. Additionally, Dr. Rojas-Cessa is the recipient of the "Excellence in Teaching Award 2013" from the Newark College of Engineering at NJIT. He is a Senior Member of IEEE and a Member of ACM. He has taught Introduction to Computer Architecture, Internet and Higher Layer Protocols, and High Performance Routers and Switches for over 10 years.

• Part I: Processor Interconnections. Multiprocessor Interconnection Networks. Routing. Part II: Data Networks. Internet Protocol (IP) Address Lookup. Packet Classification. Basics of Packet Switching. Input-Queued Switches. Shared-Memory Packet Switches. Load-Balancing Switches. Clos-Network Packet Switches. Buffer Management in Routers. Part III: Data-Center Networks. Data Center Networks.

"The organization of the book is very convenient. It is easy to read each part separately. Moving around the book is easy with a table of contents at the beginning of the book and separate tables of contents starting each chapter. In addition, every chapter ends with sample exercises. All parts of the book are richly illustrated with numerous figures. According to the saying that one image is worth a thousand words, drawings make it much easier for a reader to follow the discussion.The book ends with a very solid bibliography containing 191 positions. The largest part of the bibliography gathers positions from the 1990s and 2000s, but some positions from the three most recent years are also included. Interested readers will then be able to broaden their self-studies on interconnection networks. The bibliography is followed by the useful terms index. In my opinion, this book is mostly aimed at undergraduate students interested in modern telecommunication and computer networks. Nevertheless, graduate students will also find this book a helpful textbook for their learning efforts."—IEEE Communications Magazine, July 2017 Issue