Roberto Gastaldi was born in Reggio Emilia, Italy in 1953. He received the laurea degree in Electronic Engineering from Politecnico of Milano in 1977. He attended a postgraduate course in solid-state physics at Perugia University in 1978 and a postgraduate course in Business management at Bocconi University (Milano) in 1995. In 1977 he joined SGS-ATES (later STMicrolectronics) in Agrate Brianza (Milano) where he was involved as a device engineer in central R&D department. In 1980 he moved to memory design team working on first EPROM and EEPROM products development and later as a responsible of EPROM design team he was in charge of the EPROM family design scaling roadmap. He was involved in early 256K to 8Mb Flash-NOR product development and as a member of technical staff he contributed to industrialization of first Flash-NOR products In 2000 he took the lead of RAM design team to design SRAM and PSRAM to be used in MCP products creating from scratch a 512K-16Mb SRAM and 32-64-128Mb PSRAM product family In 2003 he started to work on PCRAM technology development and in 2006 was co-owner of the first 128Mb PCM product worldwide in 90nm technology. In 2008 he joined Micron Semiconductor and was responsible for Emerging Memory design team, since then he made evaluations and feasibility studies on different emerging memory technologies such as T-RAM, Fe-RAM, STT-RAM. His present interests are on smart Error Correction architectures and 3D memory systems. Mr. Gastaldi owns more than 50 US granted patents and a number of publications concerning NVM design. He served as a member of ISSCC International technical Memory subcommittee from 2009 to 2011 and he chaired ISSCC2010 non-volatile memory session in 2010. He was a member of the winner team of “innovator of the year” award for EDN in 2009. Mr. Gastaldi has been a lecturer on selected topics on Microelectronics at Pavia University in 2008-2014 and since 2014 he is a member of CatreneApplication steering group. Mr. Gastaldi is a member of IEEE Giovanni Campardo was born in Bergamo, Italy, in 1958. He received the laurea degree in Nuclear Engineering from the Politecnico of Milan in 1984. In 1997 he graduated in physics from the Universita’ Statale di Milano, Milan. After a short experience in the field of laser in 1984, he joined in the VLSI division of SGS (now STMicroelectronics) Milan, where, as a Project Leader, he designed the family of EPROM nMOS devices (512k, 256k, 128k and 64k) and a Look-up-table-based EPROM FIR in CMOS technology. From 1988 to 1992, after resigning from STMicroelectronics, he worked as an ASIC designer, realizing four devices. In 1992 he joined STMicroelectronics again, concentrating on Flash memory design for the microcontroller division, as a Project leader. Here he has realized a Flash + SRAM memory device for automotive applications and two embedded Flash memories (256k and 1M) for ST10 microcontrollerfamily. Since 1994 he has been responsible for Flash memory design inside the Memory Division of SGS-Thomson Microelectronics where he has realized two double-supply Flash Memories (2M and 4M) and the single supply 8M at 1.8V. He was the Design Manager for the 64M multilevel Flash project. Up to the end of 2001 he was the Product Development Manager for the Mass Storage Flash Devices in STMicroelectronics Flash Division realizing the 128M multilevel Flash and a test pattern to store more than 2bit/cell. From 2002 to 2007, inside the ST Wireless Flash Division, he had the responsibility of building-up a team to develop 3D Integration in the direction of System-in-Package solutions. From 2007 to 2010 he was the Director of the Card Business Unit inside the Numonyx DATA NAND Flash Group. In 2010 Micron acquired Numonyx and, after a short time in Micron he moved in a company, as Design Director, for the EWS testing board design. In 2013 he joint Micron again as MANAGED MEMORY SYSTEMS MANAGER. From September 2014 he is in STM, in the Automotive Product Group, in the R&D design group. He is author/co-author of more than 100 patents and some publications and author/co-author of the books: "Flash Memories", Kluwer Academic Publishers, 1999, and the book “Floating Gate Devices: Operation and Compact Modeling”, Kluwer Academic Publishers, January 2004. Author of the book “Design of Non Volatile Memory”, Franco Angeli, 2000, and “VLSI-Design of Non-Volatile Memories”, Springer Series in ADVANCED MICROELECTRONICS, 2005.  “Memorie in Sistemi Wireless”, Franco Angeli Editore, collana scientifica, serie di Informatica, 2005. “Memories in Wireless Systems”, in CIRCUITS AND SYSTEMS, Springer Verlag, 2008. G. Campardo, F. Tiziani, M. Iaculo “Memory Mass Storage”, Springer Verlag, March 2011. He was the Co-Chairs for the “System-In-Package-Technologies” Panel discussion for the IEEE 2003 Non-Volatile Semiconductor Memory Workshop, 19th IEEE NVSMW, Monterey; Ca.  Mr. Campardo was the co-Guest Editor for the Proceeding of the IEEE, April 2003, Special issue on Flash Memory and the co-Guest Editor for the Proceeding of the IEEE, Special issue on 3D Integration Technology, January 2009. He was lecturer in the “Electronic Lab” course at the University Statale of Milan from ’96 to ’98.  In 2003, 2004 and 2005 he was the recipient for the “ST Exceptional Patent Award".

• Historical overview of solid-state non-volatile memories.- State of art limitations.- New approaches to non-volatile memories.- Core circuitry.- Periphery circuitry.- Functional interfaces.- Error management.- Algorithm to survive.- Final considerations.

Roberto Gastaldi was born in Reggio Emilia, Italy in 1953. He received the laurea degree in Electronic Engineering from Politecnico of Milano in 1977. He attended a postgraduate course in solid-state physics at Perugia University in 1978 and a postgraduate course in Business management at Bocconi University (Milano) in 1995. In 1977 he joined SGS-ATES (later STMicrolectronics) in Agrate Brianza (Milano) where he was involved as a device engineer in central R&D department. In 1980 he moved to memory design team working on first EPROM and EEPROM products development and later as a responsible of EPROM design team he was in charge of the EPROM family design scaling roadmap. He was involved in early 256K to 8Mb Flash-NOR product development and as a member of technical staff he contributed to industrialization of first Flash-NOR products In 2000 he took the lead of RAM design team to design SRAM and PSRAM to be used in MCP products creating from scratch a 512K-16Mb SRAM and 32-64-128Mb PSRAM product family In 2003 he started to work on PCRAM technology development and in 2006 was co-owner of the first 128Mb PCM product worldwide in 90nm technology. In 2008 he joined Micron Semiconductor and was responsible for Emerging Memory design team, since then he made evaluations and feasibility studies on different emerging memory technologies such as T-RAM, Fe-RAM, STT-RAM. His present interests are on smart Error Correction architectures and 3D memory systems. Mr. Gastaldi owns more than 50 US granted patents and a number of publications concerning NVM design. He served as a member of ISSCC International technical Memory subcommittee from 2009 to 2011 and he chaired ISSCC2010 non-volatile memory session in 2010. He was a member of the winner team of “innovator of the year” award for EDN in 2009. Mr. Gastaldi has been a lecturer on selected topics on Microelectronics at Pavia University in 2008-2014 and since 2014 he is a member of CatreneApplication steering group. Mr. Gastaldi is a member of IEEE Giovanni Campardo was born in Bergamo, Italy, in 1958. He received the laurea degree in Nuclear Engineering from the Politecnico of Milan in 1984. In 1997 he graduated in physics from the Universita’ Statale di Milano, Milan. After a short experience in the field of laser in 1984, he joined in the VLSI division of SGS (now STMicroelectronics) Milan, where, as a Project Leader, he designed the family of EPROM nMOS devices (512k, 256k, 128k and 64k) and a Look-up-table-based EPROM FIR in CMOS technology. From 1988 to 1992, after resigning from STMicroelectronics, he worked as an ASIC designer, realizing four devices. In 1992 he joined STMicroelectronics again, concentrating on Flash memory design for the microcontroller division, as a Project leader. Here he has realized a Flash + SRAM memory device for automotive applications and two embedded Flash memories (256k and 1M) for ST10 microcontrollerfamily. Since 1994 he has been responsible for Flash memory design inside the Memory Division of SGS-Thomson Microelectronics where he has realized two double-supply Flash Memories (2M and 4M) and the single supply 8M at 1.8V. He was the Design Manager for the 64M multilevel Flash project. Up to the end of 2001 he was the Product Development Manager for the Mass Storage Flash Devices in STMicroelectronics Flash Division realizing the 128M multilevel Flash and a test pattern to store more than 2bit/cell. From 2002 to 2007, inside the ST Wireless Flash Division, he had the responsibility of building-up a team to develop 3D Integration in the direction of System-in-Package solutions. From 2007 to 2010 he was the Director of the Card Business Unit inside the Numonyx DATA NAND Flash Group. In 2010 Micron acquired Numonyx and, after a short time in Micron he moved in a company, as Design Director, for the EWS testing board design. In 2013 he joint Micron again as MANAGED MEMORY SYSTEMS MANAGER. From September 2014 he is in STM, in the Automotive Product Group, in the R&D design group. He is author/co-author of more than 100 patents and some publications and author/co-author of the books: "Flash Memories", Kluwer Academic Publishers, 1999, and the book “Floating Gate Devices: Operation and Compact Modeling”, Kluwer Academic Publishers, January 2004. Author of the book “Design of Non Volatile Memory”, Franco Angeli, 2000, and “VLSI-Design of Non-Volatile Memories”, Springer Series in ADVANCED MICROELECTRONICS, 2005.  “Memorie in Sistemi Wireless”, Franco Angeli Editore, collana scientifica, serie di Informatica, 2005. “Memories in Wireless Systems”, in CIRCUITS AND SYSTEMS, Springer Verlag, 2008. G. Campardo, F. Tiziani, M. Iaculo “Memory Mass Storage”, Springer Verlag, March 2011. He was the Co-Chairs for the “System-In-Package-Technologies” Panel discussion for the IEEE 2003 Non-Volatile Semiconductor Memory Workshop, 19th IEEE NVSMW, Monterey; Ca.  Mr. Campardo was the co-Guest Editor for the Proceeding of the IEEE, April 2003, Special issue on Flash Memory and the co-Guest Editor for the Proceeding of the IEEE, Special issue on 3D Integration Technology, January 2009. He was lecturer in the “Electronic Lab” course at the University Statale of Milan from ’96 to ’98.  In 2003, 2004 and 2005 he was the recipient for the “ST Exceptional Patent Award".

• Historical overview of solid-state non-volatile memories.- State of art limitations.- New approaches to non-volatile memories.- Core circuitry.- Periphery circuitry.- Functional interfaces.- Error management.- Algorithm to survive.- Final considerations.

Roberto Gastaldi was born in Reggio Emilia, Italy in 1953. He received the laurea degree in Electronic Engineering from Politecnico of Milano in 1977. He attended a postgraduate course in solid-state physics at Perugia University in 1978 and a postgraduate course in Business management at Bocconi University (Milano) in 1995. In 1977 he joined SGS-ATES (later STMicrolectronics) in Agrate Brianza (Milano) where he was involved as a device engineer in central R&D department. In 1980 he moved to memory design team working on first EPROM and EEPROM products development and later as a responsible of EPROM design team he was in charge of the EPROM family design scaling roadmap. He was involved in early 256K to 8Mb Flash-NOR product development and as a member of technical staff he contributed to industrialization of first Flash-NOR products In 2000 he took the lead of RAM design team to design SRAM and PSRAM to be used in MCP products creating from scratch a 512K-16Mb SRAM and 32-64-128Mb PSRAM product family In 2003 he started to work on PCRAM technology development and in 2006 was co-owner of the first 128Mb PCM product worldwide in 90nm technology. In 2008 he joined Micron Semiconductor and was responsible for Emerging Memory design team, since then he made evaluations and feasibility studies on different emerging memory technologies such as T-RAM, Fe-RAM, STT-RAM. His present interests are on smart Error Correction architectures and 3D memory systems. Mr. Gastaldi owns more than 50 US granted patents and a number of publications concerning NVM design. He served as a member of ISSCC International technical Memory subcommittee from 2009 to 2011 and he chaired ISSCC2010 non-volatile memory session in 2010. He was a member of the winner team of “innovator of the year” award for EDN in 2009. Mr. Gastaldi has been a lecturer on selected topics on Microelectronics at Pavia University in 2008-2014 and since 2014 he is a member of CatreneApplication steering group. Mr. Gastaldi is a member of IEEE Giovanni Campardo was born in Bergamo, Italy, in 1958. He received the laurea degree in Nuclear Engineering from the Politecnico of Milan in 1984. In 1997 he graduated in physics from the Universita’ Statale di Milano, Milan. After a short experience in the field of laser in 1984, he joined in the VLSI division of SGS (now STMicroelectronics) Milan, where, as a Project Leader, he designed the family of EPROM nMOS devices (512k, 256k, 128k and 64k) and a Look-up-table-based EPROM FIR in CMOS technology. From 1988 to 1992, after resigning from STMicroelectronics, he worked as an ASIC designer, realizing four devices. In 1992 he joined STMicroelectronics again, concentrating on Flash memory design for the microcontroller division, as a Project leader. Here he has realized a Flash + SRAM memory device for automotive applications and two embedded Flash memories (256k and 1M) for ST10 microcontrollerfamily. Since 1994 he has been responsible for Flash memory design inside the Memory Division of SGS-Thomson Microelectronics where he has realized two double-supply Flash Memories (2M and 4M) and the single supply 8M at 1.8V. He was the Design Manager for the 64M multilevel Flash project. Up to the end of 2001 he was the Product Development Manager for the Mass Storage Flash Devices in STMicroelectronics Flash Division realizing the 128M multilevel Flash and a test pattern to store more than 2bit/cell. From 2002 to 2007, inside the ST Wireless Flash Division, he had the responsibility of building-up a team to develop 3D Integration in the direction of System-in-Package solutions. From 2007 to 2010 he was the Director of the Card Business Unit inside the Numonyx DATA NAND Flash Group. In 2010 Micron acquired Numonyx and, after a short time in Micron he moved in a company, as Design Director, for the EWS testing board design. In 2013 he joint Micron again as MANAGED MEMORY SYSTEMS MANAGER. From September 2014 he is in STM, in the Automotive Product Group, in the R&D design group. He is author/co-author of more than 100 patents and some publications and author/co-author of the books: "Flash Memories", Kluwer Academic Publishers, 1999, and the book “Floating Gate Devices: Operation and Compact Modeling”, Kluwer Academic Publishers, January 2004. Author of the book “Design of Non Volatile Memory”, Franco Angeli, 2000, and “VLSI-Design of Non-Volatile Memories”, Springer Series in ADVANCED MICROELECTRONICS, 2005.  “Memorie in Sistemi Wireless”, Franco Angeli Editore, collana scientifica, serie di Informatica, 2005. “Memories in Wireless Systems”, in CIRCUITS AND SYSTEMS, Springer Verlag, 2008. G. Campardo, F. Tiziani, M. Iaculo “Memory Mass Storage”, Springer Verlag, March 2011. He was the Co-Chairs for the “System-In-Package-Technologies” Panel discussion for the IEEE 2003 Non-Volatile Semiconductor Memory Workshop, 19th IEEE NVSMW, Monterey; Ca.  Mr. Campardo was the co-Guest Editor for the Proceeding of the IEEE, April 2003, Special issue on Flash Memory and the co-Guest Editor for the Proceeding of the IEEE, Special issue on 3D Integration Technology, January 2009. He was lecturer in the “Electronic Lab” course at the University Statale of Milan from ’96 to ’98.  In 2003, 2004 and 2005 he was the recipient for the “ST Exceptional Patent Award".

• Historical overview of solid-state non-volatile memories.- State of art limitations.- New approaches to non-volatile memories.- Core circuitry.- Periphery circuitry.- Functional interfaces.- Error management.- Algorithm to survive.- Final considerations.