Jung Han Choi holds a BS and MS from the Sogang University, Seoul, Korea, and Dr.-Ing from the Technische Universität München, Germany. He currently works on high-data-bit-rate transmitter and receiver circuits, active/passive device modeling, and network analyzer measurement at the Fraunhofer Heinrich-Hertz Institute, Berlin, Germany. He previously served as a research scientist in the Institute for High-Frequency Engineering at the Technische Universität München, and was with the Samsung Advanced Institute of Technology and the Samsung Digital Media and Communication Research Center. In 2003, he received the EEEfCOM Innovation Prize for his contribution to the development of a high-speed receiver circuit.

• Terahertz Technology based on Nanoelectronic Devices. Ultimate FDSOI Multigate MOSFETs and Multibarrier Boosted Gate Resonant Tunneling FETs for a New High-Performance Low-Power Paradigm. SiGe BiCMOS Technology and Devices. SiGe HBT Technology and Circuits for THz Applications. Multiwavelength Sub-THz Sensor Array with Integrated Lock-In Amplifier and Signal Processing in 90 nm CMOS Technology. 40/100 GbE Physical Layer Connectivity for Servers and Data Centers. Equalization and Multilevel Modulation for Multi-Gbps Chip-to-Chip Links. 25 G/40 G CMOS SerDes: Need, Architecture, and Implementation. Clock and Data Recovery Circuits.

"... a valuable reference for high-speed device and circuit researchers and design engineers."—James Chu, Kennesaw State University, Marietta, Georgia, USA, from IEEE Microwave Magazine, November 2015

Jung Han Choi holds a BS and MS from the Sogang University, Seoul, Korea, and Dr.-Ing from the Technische Universität München, Germany. He currently works on high-data-bit-rate transmitter and receiver circuits, active/passive device modeling, and network analyzer measurement at the Fraunhofer Heinrich-Hertz Institute, Berlin, Germany. He previously served as a research scientist in the Institute for High-Frequency Engineering at the Technische Universität München, and was with the Samsung Advanced Institute of Technology and the Samsung Digital Media and Communication Research Center. In 2003, he received the EEEfCOM Innovation Prize for his contribution to the development of a high-speed receiver circuit.

• Terahertz Technology based on Nanoelectronic Devices. Ultimate FDSOI Multigate MOSFETs and Multibarrier Boosted Gate Resonant Tunneling FETs for a New High-Performance Low-Power Paradigm. SiGe BiCMOS Technology and Devices. SiGe HBT Technology and Circuits for THz Applications. Multiwavelength Sub-THz Sensor Array with Integrated Lock-In Amplifier and Signal Processing in 90 nm CMOS Technology. 40/100 GbE Physical Layer Connectivity for Servers and Data Centers. Equalization and Multilevel Modulation for Multi-Gbps Chip-to-Chip Links. 25 G/40 G CMOS SerDes: Need, Architecture, and Implementation. Clock and Data Recovery Circuits.

"... a valuable reference for high-speed device and circuit researchers and design engineers."—James Chu, Kennesaw State University, Marietta, Georgia, USA, from IEEE Microwave Magazine, November 2015

Jung Han Choi holds a BS and MS from the Sogang University, Seoul, Korea, and Dr.-Ing from the Technische Universität München, Germany. He currently works on high-data-bit-rate transmitter and receiver circuits, active/passive device modeling, and network analyzer measurement at the Fraunhofer Heinrich-Hertz Institute, Berlin, Germany. He previously served as a research scientist in the Institute for High-Frequency Engineering at the Technische Universität München, and was with the Samsung Advanced Institute of Technology and the Samsung Digital Media and Communication Research Center. In 2003, he received the EEEfCOM Innovation Prize for his contribution to the development of a high-speed receiver circuit.

• Terahertz Technology based on Nanoelectronic Devices. Ultimate FDSOI Multigate MOSFETs and Multibarrier Boosted Gate Resonant Tunneling FETs for a New High-Performance Low-Power Paradigm. SiGe BiCMOS Technology and Devices. SiGe HBT Technology and Circuits for THz Applications. Multiwavelength Sub-THz Sensor Array with Integrated Lock-In Amplifier and Signal Processing in 90 nm CMOS Technology. 40/100 GbE Physical Layer Connectivity for Servers and Data Centers. Equalization and Multilevel Modulation for Multi-Gbps Chip-to-Chip Links. 25 G/40 G CMOS SerDes: Need, Architecture, and Implementation. Clock and Data Recovery Circuits.

"... a valuable reference for high-speed device and circuit researchers and design engineers."—James Chu, Kennesaw State University, Marietta, Georgia, USA, from IEEE Microwave Magazine, November 2015