Fundamentals of VHDL for FPGA Programming Using Vivado

Majid Pakdel received his Master’s degree in Electrical Power Engineering from Isfahan University of Technology, Iran, in 2007, his PhD in Electrical Power Engineering from University of Zanjan in 2018, and his second Masters degree in Computer Engineering-Artificial Intelligence and Robotics from Malek Ashlar University of Technology, Tehran, in 2023. He has published over 20 papers and books in the fields of electrical engineering and computer science.

• About the Author xiPreface xiiAcknowledgments xiiiAbout the Companion Website xiv1 Overview 11.1 Introduction 11.2 Introduction to VHDL 22 Creating a Project in Vivado 52.1 Introduction 52.2 Creating a Project 53 The VHDL Design Structure 133.1 Introduction 133.2 The VHDL Keywords 133.3 The VHDL Libraries 193.4 The VHDL Entities and Architecture 253.5 The VHDL Generics 274 The VHDL Statements and Data Types 314.1 Introduction 314.2 The VHDL Data Types 324.3 The VHDL Integers 354.4 The When-Else Statement 364.5 Concurrent Versus Sequential Statements 375 The Simulations in Vivado 415.1 Introduction 415.2 The Shift Register Design 425.3 Shift Register Test Bench Design 445.4 Vivado Simulator Tool Introduction 465.5 Running a Simulation in Vivado 475.6 Navigating Vivado Simulations 526 The Buttons and LEDs Project 616.1 Introduction 616.2 Buttons and LEDs Complete Design Walk-through 616.3 The Button_LED Arty A7 IO Placement 636.4 Generate a Xilinx Programming File 666.5 Simulation of Button_LED Project 717 The Blinky LEDs Project 757.1 Introduction 757.2 Constants and Signals 757.3 The VHDL Processes 787.4 The VHDL If Statements 817.5 The If Statement Priority Example 857.6 The Blinky LEDs Project IO Placement 908 The LED Brightness Project 938.1 Introduction 938.2 The PWM VHDL Design 948.3 The VHDL Generate Statement 1018.4 The Counter Design 1038.5 The VHDL Component Instantiations 1108.6 The LED Brightness Arty A7 IO Placement 1209 The UART Demonstration Project 1259.1 Introduction 1259.2 The MicroBlaze Softcore Processor 1299.3 The Xilinx Software Development Kit 1339.4 The UART Demonstration Arty A7 IO Placement 14610 The UART IO and Register Access 14910.1 Introduction 14910.2 The UART IO Complete Design 15310.3 The UART IO Arty A7 IO Placement 16011 The ADC Processing Project 16311.1 Introduction 16311.2 Using the Xilinx XADC and MicroBlaze MCS 16611.3 The MicroBlaze MCS ADC Configuration 17111.4 Interfacing with the XADC Core 17211.5 The ADC Processing Arty A7 IO Placement 18112 The SPI Interface Project 18312.1 Introduction 18312.2 Overview of the SPI Interface 18612.3 The SPI Interface Design Strategy 18912.4 External SPI Flash Chip Memory Organization 19112.5 The SPI Configuration and File Generation 19313 Some Miscellaneous Projects with Vivado 19713.1 Introduction 19713.2 The I2C Interface Project 19713.3 The VHDL CORDIC Sine-Cosine Generator 19913.4 The Trailing Edge PWM in VHDL 20413.5 The LUT-based Sine Wave in VHDL 21913.6 The Symmetrical PWM in VHDL 22914 Generating VHDL Code for Vivado Using Simulink HDL Coder 24714.1 Introduction 24714.2 The Half Adder Circuit Design 24714.3 Sequential Circuit and State Flow Chart Modeling 25314.4 The Basic PWM Design 26215 Application of Flowcharts in Simulink for VHDL Code Generation 27115.1 Flowchart of Multiplier 27115.2 Flowchart of GCD Calculator 28315.3 Flowchart of Booth’s Multiplication 29115.4 Flowchart of an Industrial Control System 29916 Machine Learning Regression Model on FPGA 31116.1 Introduction 31116.2 The Kaggle Dataset 31116.3 Machine Learning Regression Model for Admission Dataset 31116.4 The Regression Model in Simulink 31616.5 Using Generated VHDL Code in Vivado 32017 Machine Learning Binary Classification Model on FPGA 32717.1 Introduction 32717.2 The Kaggle Dataset 32717.3 The Binary Classification (Logistic Regression) 32717.4 Machine Learning Logistic Regression Model for Dataset 32917.5 The Logistic Regression Model in Simulink 33717.6 Using Generated VHDL Code in Vivado 34818 Deploying a Deep Neural Network on FPGA 35518.1 Introduction 35518.2 The Kaggle Dataset 35518.3 Introduction to Neural Networks 35518.4 Piecewise Linear Approximation of Activation Functions 35718.5 Training the Neural Network Model 36818.6 Using Generated VHDL Code in Vivado 389Index 395