Pierre-Emmanuel Gaillardon is an Assistant Professor in the Electrical and Computer Engineering Department and an adjunct assistant professor in the School of Computing at The University of Utah, Salt Lake City, USA where he leads the Laboratory for NanoIntegrated Systems (LNIS). Professor Gaillardon is recipient of the BSF 2017 Prof. Pazy Memorial Research Award, the 2018 NSF CAREER award in functionality-enhanced transistors and the 2018 IEEE CEDA Pederson Award.

• Chapter 1: Introduction to functionality-enhanced devicesPart I: Materials and device research related to functionality-enhanced devicesChapter 2: Germanium-based polarity-controllable transistorsChapter 3: Two-dimensional materials for functionality-enhanced devicesChapter 4: Wse2 polarity-controllable devicesChapter 5: Carrier type control of MX2 type 2D materials for functionality-enhanced transistorsChapter 6: Three-independent gate FET's super steep subthreshold slopeChapter 7: Super sensitive terahertz detectors Part II: Applications and design techniques of functionality-enhanced devicesChapter 8: CNT and SiNW modeling for dual-gate ambipolar logic circuit designChapter 9: Physical design of polarity controllable transistorsChapter 10: BCB benchmarking for three-independent-gate field effect transistorsChapter 11: Exploratory logic synthesis for multiple independent gate FETsChapter 12: Ultrafine grain FPGAs with polarity controllable transistorsChapter 13: Tunnel FET-based security primitive design

Pierre-Emmanuel Gaillardon is an Assistant Professor in the Electrical and Computer Engineering Department and an adjunct assistant professor in the School of Computing at The University of Utah, Salt Lake City, USA where he leads the Laboratory for NanoIntegrated Systems (LNIS). Professor Gaillardon is recipient of the BSF 2017 Prof. Pazy Memorial Research Award, the 2018 NSF CAREER award in functionality-enhanced transistors and the 2018 IEEE CEDA Pederson Award.

• Chapter 1: Introduction to functionality-enhanced devicesPart I: Materials and device research related to functionality-enhanced devicesChapter 2: Germanium-based polarity-controllable transistorsChapter 3: Two-dimensional materials for functionality-enhanced devicesChapter 4: Wse2 polarity-controllable devicesChapter 5: Carrier type control of MX2 type 2D materials for functionality-enhanced transistorsChapter 6: Three-independent gate FET's super steep subthreshold slopeChapter 7: Super sensitive terahertz detectors Part II: Applications and design techniques of functionality-enhanced devicesChapter 8: CNT and SiNW modeling for dual-gate ambipolar logic circuit designChapter 9: Physical design of polarity controllable transistorsChapter 10: BCB benchmarking for three-independent-gate field effect transistorsChapter 11: Exploratory logic synthesis for multiple independent gate FETsChapter 12: Ultrafine grain FPGAs with polarity controllable transistorsChapter 13: Tunnel FET-based security primitive design

Pierre-Emmanuel Gaillardon is an Assistant Professor in the Electrical and Computer Engineering Department and an adjunct assistant professor in the School of Computing at The University of Utah, Salt Lake City, USA where he leads the Laboratory for NanoIntegrated Systems (LNIS). Professor Gaillardon is recipient of the BSF 2017 Prof. Pazy Memorial Research Award, the 2018 NSF CAREER award in functionality-enhanced transistors and the 2018 IEEE CEDA Pederson Award.

• Chapter 1: Introduction to functionality-enhanced devicesPart I: Materials and device research related to functionality-enhanced devicesChapter 2: Germanium-based polarity-controllable transistorsChapter 3: Two-dimensional materials for functionality-enhanced devicesChapter 4: Wse2 polarity-controllable devicesChapter 5: Carrier type control of MX2 type 2D materials for functionality-enhanced transistorsChapter 6: Three-independent gate FET's super steep subthreshold slopeChapter 7: Super sensitive terahertz detectors Part II: Applications and design techniques of functionality-enhanced devicesChapter 8: CNT and SiNW modeling for dual-gate ambipolar logic circuit designChapter 9: Physical design of polarity controllable transistorsChapter 10: BCB benchmarking for three-independent-gate field effect transistorsChapter 11: Exploratory logic synthesis for multiple independent gate FETsChapter 12: Ultrafine grain FPGAs with polarity controllable transistorsChapter 13: Tunnel FET-based security primitive design