FPGA-based Implementation of Signal Processing Systems

Roger Woods is a full professor and Research Director for the Electronics and Computer Engineering Cluster at Queen's University Belfast, Northern Ireland, UK.John McAllister is an academic at Queen's University Belfast, Northern Ireland, UK.Gaye Lightbody is a Lecturer within the School of Computing and Mathematics at Ulster University, Northern Ireland, UK.Ying Yi is currently a Senior Software Engineer at SN Systems, a wholly owned subsidiary of Sony Interactive Entertainment Inc, England, UK.

• Preface xvList of Abbreviations xxi1 Introduction to Field Programmable Gate Arrays 11.1 Introduction 11.2 Field Programmable Gate Arrays 21.3 Influence of Programmability 61.4 Challenges of FPGAs 8Bibliography 92 DSP Basics 112.1 Introduction 112.2 Definition of DSP Systems 122.3 DSP Transformations 162.4 Filters 202.5 Adaptive Filtering 292.6 Final Comments 38Bibliography 383 Arithmetic Basics 413.1 Introduction 413.2 Number Representations 423.3 Arithmetic Operations 473.4 Alternative Number Representations 553.5 Division 593.6 Square Root 603.7 Fixed-Point versus Floating-Point 643.8 Conclusions 66Bibliography 674 Technology Review 704.1 Introduction 704.2 Implications of Technology Scaling 714.3 Architecture and Programmability 724.4 DSP Functionality Characteristics 744.5 Microprocessors 764.6 DSP Processors 824.7 Graphical Processing Units 864.8 System-on-Chip Solutions 884.9 Heterogeneous Computing Platforms 914.10 Conclusions 92Bibliography 925 Current FPGA Technologies 945.1 Introduction 945.2 Toward FPGAs 955.3 Altera Stratix® V and 10 FPGA Family 985.4 Xilinx UltrascaleTM/Virtex-7 FPGA Families 1035.5 Xilinx Zynq FPGA Family 1075.6 Lattice iCE40isp FPGA Family 1085.7 MicroSemi RTG4 FPGA Family 1115.8 Design Stratregies for FPGA-based DSP Systems 1125.9 Conclusions 114Bibliography 1146 Detailed FPGA Implementation Techniques 1166.1 Introduction 1166.2 FPGA Functionality 1176.3 Mapping to LUT-Based FPGA Technology 1236.4 Fixed-Coefficient DSP 1256.5 Distributed Arithmetic 1306.6 Reduced-Coefficient Multiplier 1336.7 Conclusions 137Bibliography 1387 Synthesis Tools for FPGAs 1407.1 Introduction 1407.2 High-Level Synthesis 1417.3 Xilinx Vivado 1437.4 Control Logic Extraction Phase Example 1447.5 Altera SDK for OpenCL 1457.6 Other HLS Tools 1477.7 Conclusions 150Bibliography 1508 Architecture Derivation for FPGA-based DSP Systems 1528.1 Introduction 1528.2 DSP Algorithm Characteristics 1538.3 DSP Algorithm Representations 1578.4 Pipelining DSP Systems 1608.5 Parallel Operation 1708.6 Conclusions 178Bibliography 1799 Complex DSP Core Design for FPGA 1809.1 Introduction 1809.2 Motivation for Design for Reuse 1819.3 Intellectual Property Cores 1829.4 Evolution of IP Cores 1849.5 Parameterizable (Soft) IP Cores 1879.6 IP Core Integration 1959.7 Current FPGA-based IP Cores 1979.8 Watermarking IP 1989.9 Summary 198Bibliography 19910 AdvancedModel-Based FPGA Accelerator Design 20010.1 Introduction 20010.2 Dataflow Modeling of DSP Systems 20110.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs 20410.4 Model-Based Development of Multi-Channel Dataflow Accelerators 20510.5 Model-Based Development for Memory-Intensive Accelerators 21910.6 Summary 223References 22311 Adaptive Beamformer Example 22511.1 Introduction to Adaptive Beamforming 22611.2 Generic Design Process 22611.3 Algorithm to Architecture 23111.4 Efficient Architecture Design 23511.5 Generic QR Architecture 24011.6 Retiming the Generic Architecture 24611.7 Parameterizable QR Architecture 25311.8 Generic Control 26611.9 Beamformer Design Example 26911.10 Summary 271References 27112 FPGA Solutions for Big Data Applications 27312.1 Introduction 27312.2 Big Data 27412.3 Big Data Analytics 27512.4 Acceleration 28012.5 k-Means Clustering FPGA Implementation 28312.6 FPGA-Based Soft Processors 28612.7 System Hardware 29012.8 Conclusions 293Bibliography 29313 Low-Power FPGA Implementation 29613.1 Introduction 29613.2 Sources of Power Consumption 29713.3 FPGA Power Consumption 30013.4 Power Consumption Reduction Techniques 30213.5 Dynamic Voltage Scaling in FPGAs 30313.6 Reduction in Switched Capacitance 30513.7 Final Comments 316Bibliography 31714 Conclusions 31914.1 Introduction 31914.2 Evolution in FPGA Design Approaches 32014.3 Big Data and the Shift toward Computing 32014.4 Programming Flow for FPGAs 32114.5 Support for Floating-Point Arithmetic 32214.6 Memory Architectures 322Bibliography 323Index 325