Samar K. Saha received a PhD in Physics from Gauhati University, India, andMS in Engineering Management from Stanford University, CA. Currently, he is anAdjunct Professor in the Electrical Engineering Department at Santa Clara University,CA, and Chief Research Scientist at Prospicient Devices, CA. Since 1984, he hasworked in various technical and management positions for National Semiconductor,LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology,Synopsys, DSM Solutions, Silterra USA, and SuVolta. He has also worked as afaculty member in the Electrical Engineering Departments at Southern IllinoisUniversity at Carbondale, IL; Auburn University, AL; the University of Nevada atLas Vegas, NV; and the University of Colorado at Colorado Springs, CO. He hasauthored more than 100 research papers. He has also authored one book, CompactModels for Integrated Circuit Design: Conventional Transistors and Beyond (CRCPress, 2015); one book chapter on Technology Computer-Aided Design (TCAD),“Introduction to Technology Computer-Aided Design,” in Technology ComputerAided Design: Simulation for VLSI MOSFET (C.K. Sarkar, ed., CRC Press, 2013);and holds 12 US patents. His research interests include nanoscale device and processarchitecture, TCAD, compact modeling, devices for renewable energy, and TCADand R&D management.Dr. Saha served as the 2016–2017 President of the Institute of Electrical andElectronics Engineers (IEEE) Electron Devices Society (EDS) and is currently servingas the Senior Past President of EDS, J.J. Ebers Award Committee Chair, andEDS Fellow Evaluation Committee Chair. He is a Fellow of IEEE and a Fellowof the Institution of Engineering and Technology (IET, UK), and a DistinguishedLecturer of IEEE EDS. Previously, he has served as the Junior Past President of EDS;EDS Awards Chair; EDS Fellow Evaluation Committee Member; EDS President-Elect; Vice President of EDS Publications; an elected member of the EDS Board ofGovernors; Editor-In-Chief of IEEE QuestEDS; Chair of EDS George Smith and PaulRappaport Awards; Editor of Region 5&6 EDS Newsletter; Chair of EDS CompactModeling Technical Committee; Chair of EDS North America West Subcommitteefor Regions/Chapters; a member of the IEEE Conference Publications Committee;a member of the IEEE TAB Periodicals Committee; and the Treasurer, Vice Chair,and Chair of the Santa Clara Valley-San Francisco EDS chapter.Dr. Saha served as the head guest editor for the IEEE Transactions onElectron Devices (T-ED) Special Issues (SIs) on Advanced Compact Models and45-nm Modeling Challenges and Compact Interconnect Models for Giga ScaleIntegration; and as a guest editor for the T-ED SI on Advanced Modeling of PowerDevices and their Applications and the IEEE Journal of Electron DevicesSociety (J-EDS) SI on Flexible Electronics from the Selected Extended Papers at2018 IFETC. He has also served as a member of the editorial board of the WorldJournal of Condensed Matter Physics (WJCMP), published by the ScientificResearch Publishing (SCIRP).

• Chapter 1 Introduction...........................................................................................1Chapter 2 Fundamentals of Semiconductor Physics............................................25Chapter 3 Multiple-Gate Metal-Oxide-Semiconductor (MOS) System..............85Chapter 4 Overview of FinFET Device Technology......................................... 133Chapter 5 Large Geometry FinFET Device Operation..................................... 151Chapter 7 Leakage Currents in FinFETs........................................................... 215Chapter 8 Parasitic Elements in FinFETs.......................................................... 231Chapter 9 Challenges to FinFET Process and Device Technology .................. 257Chapter 10 FinFET Compact Models for Circuit Simulation..............................277Index.......................................................................................................................309

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