KRZYSZTOF (KRIS) INIEWSKI, PhD, is managing R&D at Redlen Technologies in Vancouver, Canada. He is also President of CMOS Emerging Technologies, an organization of high-tech events covering communications, microsystems, optoelectronics, and sensors. Dr. Iniewski has also held numerous faculty and management positions at University of Toronto, University of Alberta, Simon Fraser University, and PMC-Sierra, Inc. He has published over 100 research papers in international journals and has written and edited several books.

• Preface xvContributors xvii1 Low Power Multicore Processors for Embedded Systems 1Fumio Arakawa1.1 Multicore Chip with Highly Efficient Cores 11.2 SuperH RISC Engine Family (SH) Processor Cores 51.3 SH-X: A Highly Efficient CPU Core 91.4 SH-X FPU: A Highly Efficient FPU 201.5 SH-X2: Frequency and Efficiency Enhanced Core 331.6 SH-X3: Multicore Architecture Extension 341.7 SH-X4: ISA and Address Space Extension 472 Special-Purpose Hardware for Computational Biology 61Siddharth Srinivasan2.1 Molecular Dynamics Simulations on Graphics Processing Units 622.2 Special-Purpose Hardware and Network Topologies for MD Simulations 722.3 Quantum MC Applications on Field-Programmable Gate Arrays 772.4 Conclusions and Future Directions 823 Embedded GPU Design 85Byeong-Gyu Nam and Hoi-Jun Yoo3.1 Introduction 853.2 System Architecture 863.3 Graphics Modules Design 883.4 System Power Management 953.5 Implementation Results 993.6 Conclusion 1024 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors 107Tareq Hasan Khan and Khan Wahid4.1 Introduction 1074.2 The DVP Interface 1084.3 The iBRIDGE-BB Architecture 1094.4 Hardware Implementation 1164.5 Conclusion 1235 Embedded Computing Systems on FPGAs 127Lesley Shannon5.1 FPGA Architecture 1285.2 FPGA Confi guration Technology 1295.3 Software Support 1335.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs 1356 FPGA-Based Emulation Support for Design Space Exploration 139Paolo Meloni, Simone Secchi, and Luigi Raffo6.1 Introduction 1396.2 State of the Art 1406.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience 1446.4 Enabling FPGA-Based DSE: Runtime-Reconfi gurable Emulators 1476.5 Use Cases 1617 FPGA Coprocessing Solution for Real-Time Protein Identifi cation Using Tandem Mass Spectrometry 169Daniel Coca, István Bogdán, and Robert J. Beynon7.1 Introduction 1697.2 Protein Identifi cation by Sequence Database Searching Using MS/MS Data 1717.3 Reconfi gurable Computing Platform 1747.4 FPGA Implementation of the MS/MS Search Engine 1767.5 Summary 1808 Real-Time Confi gurable Phase-Coherent Pipelines 185Robert L. Shuler, Jr., and David K. Rutishauser8.1 Introduction and Purpose 1858.2 History and Related Methods 1888.3 Implementation Framework 1918.4 Prototype Implementation 2048.5 Assessment Compared with Related Methods 2079 Low Overhead Radiation Hardening Techniques for Embedded Architectures 211Sohan Purohit, Sai Rahul Chalamalasetti, and Martin Margala9.1 Introduction 2119.2 Recently Proposed SEU Tolerance Techniques 2139.3 Radiation-Hardened Reconfi gurable Array with Instruction Rollback 2239.4 Conclusion 23410 Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip 239Sudeep Pasricha and Yong Zou10.1 Introduction 23910.2 Related Work 24010.3 Proposed 4NP-First Routing Scheme 24210.4 Experiments 25010.5 Conclusion 25511 Interoperability in Electronic Systems 259Andrew Leone11.1 Interoperability 25911.2 The Basis for Interoperability: The OSI Model 26111.3 Hardware 26311.4 Firmware 26611.5 Partitioning the System 26811.6 Examples of Interoperable Systems 27012 Software Modeling Approaches for Presilicon System Performance Analysis 273Kenneth J. Schultz and Frederic Risacher12.1 Introduction 27312.2 Methodologies 27512.3 Results 28312.4 Conclusion 28813 Advanced Encryption Standard (AES) Implementation in Embedded Systems 291Issam Hammad, Kamal El-Sankary, and Ezz El-Masry13.1 Introduction 29113.2 Finite Field 29213.3 The AES 29313.4 Hardware Implementations for AES 30013.5 High-Speed AES Encryptor with Efficient Merging Techniques 30613.6 Conclusion 31514 Reconfi gurable Architecture for Cryptography over Binary Finite Fields 319Samuel Antão, Ricardo Chaves, and Leonel Sousa14.1 Introduction 31914.2 Background 32014.3 Reconfigurable Processor 33314.4 Results 35014.5 Conclusions 358References 359Index 363

KRZYSZTOF (KRIS) INIEWSKI, PhD, is managing R&D at Redlen Technologies in Vancouver, Canada. He is also President of CMOS Emerging Technologies, an organization of high-tech events covering communications, microsystems, optoelectronics, and sensors. Dr. Iniewski has also held numerous faculty and management positions at University of Toronto, University of Alberta, Simon Fraser University, and PMC-Sierra, Inc. He has published over 100 research papers in international journals and has written and edited several books.

• Preface xvContributors xvii1 Low Power Multicore Processors for Embedded Systems 1Fumio Arakawa1.1 Multicore Chip with Highly Efficient Cores 11.2 SuperH RISC Engine Family (SH) Processor Cores 51.3 SH-X: A Highly Efficient CPU Core 91.4 SH-X FPU: A Highly Efficient FPU 201.5 SH-X2: Frequency and Efficiency Enhanced Core 331.6 SH-X3: Multicore Architecture Extension 341.7 SH-X4: ISA and Address Space Extension 472 Special-Purpose Hardware for Computational Biology 61Siddharth Srinivasan2.1 Molecular Dynamics Simulations on Graphics Processing Units 622.2 Special-Purpose Hardware and Network Topologies for MD Simulations 722.3 Quantum MC Applications on Field-Programmable Gate Arrays 772.4 Conclusions and Future Directions 823 Embedded GPU Design 85Byeong-Gyu Nam and Hoi-Jun Yoo3.1 Introduction 853.2 System Architecture 863.3 Graphics Modules Design 883.4 System Power Management 953.5 Implementation Results 993.6 Conclusion 1024 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors 107Tareq Hasan Khan and Khan Wahid4.1 Introduction 1074.2 The DVP Interface 1084.3 The iBRIDGE-BB Architecture 1094.4 Hardware Implementation 1164.5 Conclusion 1235 Embedded Computing Systems on FPGAs 127Lesley Shannon5.1 FPGA Architecture 1285.2 FPGA Confi guration Technology 1295.3 Software Support 1335.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs 1356 FPGA-Based Emulation Support for Design Space Exploration 139Paolo Meloni, Simone Secchi, and Luigi Raffo6.1 Introduction 1396.2 State of the Art 1406.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience 1446.4 Enabling FPGA-Based DSE: Runtime-Reconfi gurable Emulators 1476.5 Use Cases 1617 FPGA Coprocessing Solution for Real-Time Protein Identifi cation Using Tandem Mass Spectrometry 169Daniel Coca, István Bogdán, and Robert J. Beynon7.1 Introduction 1697.2 Protein Identifi cation by Sequence Database Searching Using MS/MS Data 1717.3 Reconfi gurable Computing Platform 1747.4 FPGA Implementation of the MS/MS Search Engine 1767.5 Summary 1808 Real-Time Confi gurable Phase-Coherent Pipelines 185Robert L. Shuler, Jr., and David K. Rutishauser8.1 Introduction and Purpose 1858.2 History and Related Methods 1888.3 Implementation Framework 1918.4 Prototype Implementation 2048.5 Assessment Compared with Related Methods 2079 Low Overhead Radiation Hardening Techniques for Embedded Architectures 211Sohan Purohit, Sai Rahul Chalamalasetti, and Martin Margala9.1 Introduction 2119.2 Recently Proposed SEU Tolerance Techniques 2139.3 Radiation-Hardened Reconfi gurable Array with Instruction Rollback 2239.4 Conclusion 23410 Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip 239Sudeep Pasricha and Yong Zou10.1 Introduction 23910.2 Related Work 24010.3 Proposed 4NP-First Routing Scheme 24210.4 Experiments 25010.5 Conclusion 25511 Interoperability in Electronic Systems 259Andrew Leone11.1 Interoperability 25911.2 The Basis for Interoperability: The OSI Model 26111.3 Hardware 26311.4 Firmware 26611.5 Partitioning the System 26811.6 Examples of Interoperable Systems 27012 Software Modeling Approaches for Presilicon System Performance Analysis 273Kenneth J. Schultz and Frederic Risacher12.1 Introduction 27312.2 Methodologies 27512.3 Results 28312.4 Conclusion 28813 Advanced Encryption Standard (AES) Implementation in Embedded Systems 291Issam Hammad, Kamal El-Sankary, and Ezz El-Masry13.1 Introduction 29113.2 Finite Field 29213.3 The AES 29313.4 Hardware Implementations for AES 30013.5 High-Speed AES Encryptor with Efficient Merging Techniques 30613.6 Conclusion 31514 Reconfi gurable Architecture for Cryptography over Binary Finite Fields 319Samuel Antão, Ricardo Chaves, and Leonel Sousa14.1 Introduction 31914.2 Background 32014.3 Reconfigurable Processor 33314.4 Results 35014.5 Conclusions 358References 359Index 363

KRZYSZTOF (KRIS) INIEWSKI, PhD, is managing R&D at Redlen Technologies in Vancouver, Canada. He is also President of CMOS Emerging Technologies, an organization of high-tech events covering communications, microsystems, optoelectronics, and sensors. Dr. Iniewski has also held numerous faculty and management positions at University of Toronto, University of Alberta, Simon Fraser University, and PMC-Sierra, Inc. He has published over 100 research papers in international journals and has written and edited several books.

• Preface xvContributors xvii1 Low Power Multicore Processors for Embedded Systems 1Fumio Arakawa1.1 Multicore Chip with Highly Efficient Cores 11.2 SuperH RISC Engine Family (SH) Processor Cores 51.3 SH-X: A Highly Efficient CPU Core 91.4 SH-X FPU: A Highly Efficient FPU 201.5 SH-X2: Frequency and Efficiency Enhanced Core 331.6 SH-X3: Multicore Architecture Extension 341.7 SH-X4: ISA and Address Space Extension 472 Special-Purpose Hardware for Computational Biology 61Siddharth Srinivasan2.1 Molecular Dynamics Simulations on Graphics Processing Units 622.2 Special-Purpose Hardware and Network Topologies for MD Simulations 722.3 Quantum MC Applications on Field-Programmable Gate Arrays 772.4 Conclusions and Future Directions 823 Embedded GPU Design 85Byeong-Gyu Nam and Hoi-Jun Yoo3.1 Introduction 853.2 System Architecture 863.3 Graphics Modules Design 883.4 System Power Management 953.5 Implementation Results 993.6 Conclusion 1024 Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors 107Tareq Hasan Khan and Khan Wahid4.1 Introduction 1074.2 The DVP Interface 1084.3 The iBRIDGE-BB Architecture 1094.4 Hardware Implementation 1164.5 Conclusion 1235 Embedded Computing Systems on FPGAs 127Lesley Shannon5.1 FPGA Architecture 1285.2 FPGA Confi guration Technology 1295.3 Software Support 1335.4 Final Summary of Challenges and Opportunities for Embedded Computing Design on FPGAs 1356 FPGA-Based Emulation Support for Design Space Exploration 139Paolo Meloni, Simone Secchi, and Luigi Raffo6.1 Introduction 1396.2 State of the Art 1406.3 A Tool for Energy-Aware FPGA-Based Emulation: The MADNESS Project Experience 1446.4 Enabling FPGA-Based DSE: Runtime-Reconfi gurable Emulators 1476.5 Use Cases 1617 FPGA Coprocessing Solution for Real-Time Protein Identifi cation Using Tandem Mass Spectrometry 169Daniel Coca, István Bogdán, and Robert J. Beynon7.1 Introduction 1697.2 Protein Identifi cation by Sequence Database Searching Using MS/MS Data 1717.3 Reconfi gurable Computing Platform 1747.4 FPGA Implementation of the MS/MS Search Engine 1767.5 Summary 1808 Real-Time Confi gurable Phase-Coherent Pipelines 185Robert L. Shuler, Jr., and David K. Rutishauser8.1 Introduction and Purpose 1858.2 History and Related Methods 1888.3 Implementation Framework 1918.4 Prototype Implementation 2048.5 Assessment Compared with Related Methods 2079 Low Overhead Radiation Hardening Techniques for Embedded Architectures 211Sohan Purohit, Sai Rahul Chalamalasetti, and Martin Margala9.1 Introduction 2119.2 Recently Proposed SEU Tolerance Techniques 2139.3 Radiation-Hardened Reconfi gurable Array with Instruction Rollback 2239.4 Conclusion 23410 Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip 239Sudeep Pasricha and Yong Zou10.1 Introduction 23910.2 Related Work 24010.3 Proposed 4NP-First Routing Scheme 24210.4 Experiments 25010.5 Conclusion 25511 Interoperability in Electronic Systems 259Andrew Leone11.1 Interoperability 25911.2 The Basis for Interoperability: The OSI Model 26111.3 Hardware 26311.4 Firmware 26611.5 Partitioning the System 26811.6 Examples of Interoperable Systems 27012 Software Modeling Approaches for Presilicon System Performance Analysis 273Kenneth J. Schultz and Frederic Risacher12.1 Introduction 27312.2 Methodologies 27512.3 Results 28312.4 Conclusion 28813 Advanced Encryption Standard (AES) Implementation in Embedded Systems 291Issam Hammad, Kamal El-Sankary, and Ezz El-Masry13.1 Introduction 29113.2 Finite Field 29213.3 The AES 29313.4 Hardware Implementations for AES 30013.5 High-Speed AES Encryptor with Efficient Merging Techniques 30613.6 Conclusion 31514 Reconfi gurable Architecture for Cryptography over Binary Finite Fields 319Samuel Antão, Ricardo Chaves, and Leonel Sousa14.1 Introduction 31914.2 Background 32014.3 Reconfigurable Processor 33314.4 Results 35014.5 Conclusions 358References 359Index 363