Computer Architecture

Behrooz Parhami is Professor of Computer Engineering at the University of California, Santa Barbara. He has written several textbooks, including Computer Arithmetic (OUP, 2000), and more than 200 research papers. He is a fellow of both the Institute of Electrical and Electronics Engineers (IEEE) and the British Computer Society (BCS). He is a member of the Association for Computing Machinery (ACM), and a distinguished member of the InformaticsSociety of Iran, for which he served as a founding member and the first president.

• PrefacePART 1: BACKGROUND AND MOTIVATION1. Combinational Digital Circuits1.1.: Signals, Logic Operators, and Gates1.2.: Boolean Functions and Expressions1.3.: Designing Gate Networks1.4.: Useful Combinational Parts1.5.: Programmable Combinational Parts1.6.: Timing and Circuit Considerations2. Digital Circuits with Memory2.1.: Latches, Flip-Flops, and Registers2.2.: Finite-State Machines2.3.: Designing Sequential Circuits2.4.: Useful Sequential Parts2.5.: Programmable Sequential Parts2.6.: Clocks and Timing of Events3. Computer System Technology3.1.: From Components to Applications3.2.: Computer Systems and Their Parts3.3.: Generations of Progress3.4.: Processor and Memory Technologies3.5.: Peripherals, I/O, and Communications3.6.: Software Systems and Applications4. Computer Performance4.1.: Cost, Performance, and Cost/Performance4.2.: Defining Computer Performance4.3.: Performance Enhancement and Amdahl's Law4.4.: Performance Measurement vs.4.5.: Reporting Computer Performance4.6.: The Quest for Higher PerformancePART 2: INSTRUCTION-SET ARCHITECTURE5. Instructions and Addressing5.1.: Abstract View of Hardware5.2.: Instruction Formats5.3.: Simple Arithmetic and Logic Instructions5.4.: Load and Store Instructions5.5.: Jump and Branch Instructions5.6.: Addressing Modes6. Procedures and Data6.1.: Simple Procedure Calls6.2.: Using the Stack for Data Storage6.3.: Parameters and Results6.4.: Data Types6.5.: Arrays and Pointers6.6.: Additional Instructions7. Assembly Language Programs7.1.: Machine and Assembly Languages7.2.: Assembler Directives7.3.: Pseudoinstructions7.4.: Macroinstructions7.5.: Linking and Loading7.6.: Running Assembler Programs8. Instruction-Set Variations8.1.: Complex Instructions8.2.: Alternative Addressing Modes8.3.: Variations in Instruction Formats8.4.: Instruction Set Design and Evolution8.5.: The RISC/CISC Dichotomy8.6.: Where to Draw the LinePART 3: THE ARITHMETIC/LOGIC UNIT9. Number Representation9.1.: Positional Number Systems9.2.: Digit Sets and Encodings9.3.: Number-Radix Conversion9.4.: Signed Integers9.5.: Fixed-Point Numbers9.6.: Floating-Point Numbers10. Adders and Simple ALUs10.1.: Simple Adders10.2.: Carry Propagation Networks10.3.: Counting and Incrementation10.4.: Design of Fast Adders10.5.: Logic and Shift Operations10.6.: Multifunction ALUs11. Multipliers and Dividers11.1.: Shift-Add Multiplication11.2.: Hardware Multipliers11.3.: Programmed Multiplication11.4.: Shift-Subtract Division11.5.: Hardware Dividers11.6.: Programmed Division12. Floating-Point Arithmetic12.1.: Rounding Modes12.2.: Special Values and Exceptions12.3.: Floating-Point Addition12.4.: Other Floating-Point Operations12.5.: Floating-Point Instructions12.6.: Result Precision and ErrorsPART 4: DATA PATH AND CONTROL13. Instruction Execution Steps13.1.: A Small Set of Instructions13.2.: The Instruction Execution Unit13.3.: A Single-Cycle Data Path13.4.: Branching and Jumping13.5.: Deriving the Control Signals13.6.: Performance of the Single-Cycle Design14. Control Unit Synthesis14.1.: A Multicycle Implementation14.2.: Clock Cycle and Control Signals14.3.: The Control State Machine14.4.: Performance of the Multicycle Design14.5.: Microprogramming14.6.: Dealing with Exceptions15. Pipelined Data Paths15.1.: Pipelining Concepts15.2.: Pipeline Stalls or Bubbles15.3.: Pipeline Timing and Performance15.4.: Pipelined Data Path Design15.5.: Pipelined Control15.6.: Optimal Pipelining16. Pipeline Performance Limits16.1.: Data Dependencies and Hazards16.2.: Data Forwarding16.3.: Pipeline Branch Hazards16.4.: Branch Prediction16.5.: Advanced Pipelining16.6.: Exceptions in a PipelinePART 5: MEMORY SYSTEM DESIGN17. Main Memory Concepts17.1.: Memory Structure and SRAM17.2.: DRAM and Refresh Cycles17.3.: Hitting the Memory Wall17.4.: Pipelined and Interleaved Memory17.5.: Nonvolatile Memory17.6.: The Need for a Memory Hierarchy18. Cache Memory Organization18.1.: The Need for a Cache18.2.: What Makes a Cache Work?18.3.: Direct-Mapped Cache18.4.: Set-Associative Cache18.5.: Cache and Main Memory18.6.: Improving Cache Performance19. Mass Memory Concepts19.1.: Disk Memory Basics19.2.: Organizing Data on Disk19.3.: Disk Performance19.4.: Disk Caching19.5.: Disk Arrays and RAID19.6.: Other Types of Mass Memory20. Virtual Memory and Paging20.1.: The Need for Virtual Memory20.2.: Address Translation in Virtual Memory20.3.: Translation Lookaside Buffer20.4.: Page Replacement Policies20.5.: Main and Mass Memories20.6.: Improving Virtual Memory PerformancePART 6: INPUT/OUTPUT AND INTERFACING21. Input/Output Devices21.1.: Input/Output Devices and Controllers21.2.: Keyboard and Mouse21.3.: Visual Display Units21.4.: Hard-Copy Input/Output Devices21.5.: Other Input/Output Devices21.6.: Networking of Input/Output Devices22. Input/Output Programming22.1.: I/O Performance and Benchmarks22.2.: Input/Output Addressing22.3.: Scheduled I/O: Polling22.4.: Demand-Based I/O: Interrupts22.5.: I/O Data Transfer and DMA22.6.: Improving I/O Performance23. Buses, Links, and Interfacing23.1.: Intra- and Intersystem Links23.2.: Buses and Their Appeal23.3.: Bus Communication Protocols23.4.: Bus Arbitration and Performance23.5.: Basics of Interfacing23.6.: Interfacing Standards24. Context Switching and Interrupts24.1.: System Calls for I/O24.2.: Interrupts, Exceptions, and Traps24.3.: Simple Interrupt Handling24.4.: Nested Interrupts24.5.: Types of Context Switching24.6.: Threads and MultithreadingPART 7: ADVANCED ARCHITECTURES25. Road to Higher Performance25.1.: Past and Current Performance Trends25.2.: Performance-Driven ISA Extensions25.3.: Instruction-Level Parallelism25.4.: Speculation and Value Prediction25.5.: Special-Purpose Hardware Accelerators25.6.: Vector, Array, and Parallel Processing26. Vector and Array Processing26.1.: Operations on Vectors26.2.: Vector Processor Implementation26.3.: Vector Processor Performance26.4.: Shared-Control Systems26.5.: Array Processor Implementation26.6.: Array Processor Performance27. Shared-Memory Multiprocessing27.1.: Centralized Shared Memory27.2.: Multiple Caches and Cache Coherence27.3.: Implementing Symmetric Multiprocessors27.4.: Distributed Shared Memory27.5.: Directories to Guide Data Access27.6.: Implementing Asymmetric Multiprocessors28. Distributed Multicomputing28.1.: Communication by Message Passing28.2.: Interconnection Networks28.3.: Message Composition and Routing28.4.: Building and Using Multicomputers28.5.: Network-Based Distributed Computing28.6.: Grid Computing and BeyondIndex