Advanced Frequency Synthesis by Phase Lock

WILLIAM F. EGAN, PHD, is a lecturer in electrical engineering at Santa Clara University, California. Formerly, he was a principal engineer at TRW ESL and a senior technologist at GTE Government Systems.

• Preface xvSymbols List and Glossary xix1 Introduction 11.1 Phase-Locked Synthesizer 21.2 Fractional-N Frequency Synthesis 31.3 Representing a Change in Divide Number 31.4 Units 51.5 Representing Phase Noise 51.6 Phase Noise at the Synthesizer Output 71.7 Observing the Output Spectrum 72 Fractional-N and Basic ΣΔ Synthesizers 92.1 First-Order Fractional-N 92.1.1 Canceling Quantization Noise 112.1.2 Cancellation with a PFD 132.1.3 Cancellation Techniques 152.1.4 Spectrum without Cancellation 162.1.5 Influence of N 172.2 Second-Order Fractional-N 172.2.1 Purpose 172.2.2 Form 182.2.3 Performance 192.2.4 Interpreting the Spectrum 212.3 Higher Order Fractional-N 242.3.1 Constant Sampling Rate 252.3.2 Noise Shaping Versus Cancellation 282.3.3 Effect of a Varying Sampling Rate 282.4 Spectrums with Constant Sampling Rate 312.4.1 100.625 MHz with Zero Initial Condition 312.4.2 100.62515... with Zero Initial Condition 342.4.3 100.625 MHz with Seed 362.5 Summary of Spectrums 362.6 Summary 363 Other Spurious Reduction Techniques 393.1 LSB Dither 393.2 Maximum Sequence Length 433.3 Shortened Accumulators and Lower Primes 483.4 Long Sequence 513.5 Summary 534 Defects in ΣΔ Synthesizers 554.1 Noise Models 554.1.1 VCO Noise 554.1.2 Basic-Reference Noise 564.1.3 Equivalent Input Noise 564.1.4 ΣΔ Quantization Noise 574.1.5 Parameter Dependence 574.1.6 Synthesizer Output Noise 574.1.6.1 Nominal Parameters 594.1.6.2 Higher Fout 604.1.6.3 Higher Fref 624.1.6.4 Summary 634.2 Levels of Other Noise in ΣΔ Synthesizers 644.2.1 Dither 654.2.2 Varying Sample Rate 654.2.3 Mismatched (Unbalanced) Charge Pumps 664.2.4 Levels for All Four Loop Configurations 674.2.5 Simple Charge Pump 694.2.6 System Performance 714.3 Noise Sources, Equivalent Input Noise 714.3.1 Without ΣΔ Modulation 724.3.2 Increase with ΣΔ Modulation 734.4 Discrete Sidebands 744.4.1 At Offsets Related to ffract 744.4.1.1 Due to Current Mismatch 744.4.1.2 Not Necessarily Related to Mismatch 754.4.2 At Offsets of nFref 754.4.2.1 Due to SD Modulation 764.4.2.2 Due to Delays in the PFD 774.4.2.3 Due to Leakage Current 774.4.2.4 Due to All Three 774.4.2.5 With Resampling 784.4.2.6 Significance of Levels 784.4.3 Charge Pump Dead Zone 804.5 Summary 805 Other ΣΔ Architectures 815.1 Stability 815.2 Feedback 825.3 Feedforward 855.4 Quantizer Offset 895.5 MASH-n1n2n3 915.6 Cancellation of Quantization Noise in the General Modulator 925.7 Fractional Swallows 935.7.1 Resulting Spurs 965.7.2 Estimate of Achievable Suppression 965.7.3 Fractional Swallows in a ΣΔ Synthesizer 965.8 Hardware Reduction 975.8.1 Analysis 975.8.2 Simulation 1006 Simulation 1036.1 SandH.mdl 1036.1.1 The Synthesizer Loop 1056.1.2 MASH Modulator 1056.1.3 Setting Parameters 1056.1.4 Accumulator Size 1066.1.5 Scopes 1076.1.6 Spectrum Analyzers 1076.1.7 Spectrums Observed 1086.1.8 Reason for Frequency Conversion 1106.1.9 Synchronization 1116.2 SandHreverse.mdl 1116.3 CPandI.mdl 1116.4 Dither.mdl 1116.5 HandK.mdl 1136.6 SimplePD.mdl 1146.7 CPandIplus.mdl 1146.7.1 CP Balance 1146.7.2 PFD Delays 1166.7.3 Data Acquisition 1166.7.4 Log Plots 1166.8 CPandITrunc.mdl 1176.9 Adapting a Model 1186.10 EFeedback.mdl 1186.11 FeedForward.mdl 1206.12 MASH modulator scripts 1206.13 SynStep__.mdl 1216.14 Other Methods 1217 Diophantine Synthesizer 1237.1 Two-Loop Synthesizer 1247.2 Multi Loop Synthesizers 1267.3 MATLAB Scripts 1267.3.1 loop2tune 1267.3.2 loopxtune 1287.3.3 Algorithm 1287.4 Signal Mixing 1297.5 Reference-Frequency Coupling 1327.6 Center Frequencies 1338 Operation at Extreme Bandwidths 1358.1 Determining the Effects of Sampling 1358.2 A Particular Case 1368.3 When are Sampling Effects Important? 1418.4 Computer Program 1418.5 Sampling Effects in ΣΔ Synthesizers 1419 All-Digital Frequency Synthesizers 1459.1 The Flying Adder Synthesizer 1469.1.1 The Concept 1469.1.2 Frequencies Generated 1479.1.3 Jitter 1499.1.4 Suppression of Spurs 1509.1.5 Further Development 1519.2 ADPLL Synthesizer 1519.2.1 ADPLL Concept 1519.2.2 The Numbers 1529.2.3 Mathematical Representation 1529.2.4 DCO 1539.2.5 Loop Filter 1549.2.6 Synchronization 1549.2.7 Phase Noise 1549.2.7.1 In-Band Noise, Critical Source 1549.2.7.2 Improving Resolution 1559.2.8 Reference Spurs 1579.2.9 Fractional Spurs 1579.2.10 Modulation Response 1599.2.11 ΣΔ Cancellation 1599.2.12 Simulation 1599.2.13 Dead Zone 160Appendix A. All Digital 163A.1 Flying Adder Circuits 163A.2 ADPLL Synthesizer 164A.2.1 Alternative Architecture 164A.2.2 Reference Jitter and the Dead Zone 165A.2.3 Reference Jitter and Calibration 167A.2.4 Initial Plan for a Model of an ADPLL Synthesizer 168Appendix C. Fractional Cancellation 171C.1 Modulator Details 171C.2 First Accumulator 173C.3 Second Accumulator 173C.4 Additional Accumulators 174C.5 Accumulator without Input Register 176Appendix E. Excess PPSD 177E.1 Development of Eq. (2.4) 177E.2 Approximating kp as constant 180E.3 Approximation in Eq. (E.8) 181Appendix F. References to FS2 183Appendix G. Using GSMPL 185G.1 Open-Loop Transfer Function 185G.1.1 Without Sampling 185G.1.2 Using Gsmpl 186G.1.3 Sampling Effects 186G.2 Closed-Loop Responses 187G.3 Saving Results 187G.4 Version Number 187G.5 Example Session 187G.6 Generating Analysis Plots 189G.7 Verification of Gardner’s Stability Limits 191G.8 The Nyquist Plot 192G.8.1 Without Sampling 193G.8.2 With Sampling 193Appendix H. Sample-and-Hold Circuit 195H.1 Transient Performance 195H.1.1 No Sampling 196H.1.2 Ideal Sampler 196H.1.3 Hold with Integrator 196H.1.4 Modified Hold with Integrator 200H.2 Filter Capacitor Before Sampler 202Appendix L. Loop Response 207L.1 Primary Loop 207L.1.1 Open-Loop Transfer Function 207L.1.2 Error Transfer Function 208L.1.3 Forward Transfer Function 209L.1.4 Output PPSD Shape 211L.2 Damped Loop 213Appendix M. Mash PSD 215M.1 MASH Modulator: First Stage 217M.2 MASH Modulator: Second Order 219M.3 MASH Modulator: Higher Order 219M.4 Variances 221M.5 Some Parameters of S 222M.6 Previous Development 222M.7 Some MASH Modulator Characteristics 222M.8 Characteristics of MATLAB scripts mashone and mashall_ 223Appendix N. Sampled Noise 225N.1 Case 1: Wn ≪ fref 225N.2 Case 2: 1/ T ≫ Wn ≫ fref 225N.3 Case 3: Wn ≫ 1/ T ≫ fref 226N.4 Variance of Sampled Noise (1/ T ≫ fref) 226N.5 Convolution of PSDs 227N.6 Representing Squared PSDs 228Appendix O. Oscillator Spectrums 229Appendix P. Phase Detectors 231Appendix Q. Quantization PPSD 233Q.1 Development of Eq. (Q.1) 234Q.2 Superposition 235Q.3 New Synthesized Frequency 236Q.4 Loop Response 237Q.5 Verification of the Effect of Sampling on the Loop 237Appendix R. Reference Frequency Spurs 241R.1 Leakage Current 242R.2 Pulse Offset 242R.3 ΣΔ Modulation 243R.4 Effect of ΣΔ Modulation on Pulse Offset Spurs 244R.5 Effect of ΣΔ Modulation on Leakage Spurs 247R.6 Effects of Resampling 247Appendix S. Spectrum Analysis 249S.1 Spectrums 249S.1.1 Periodicity 249S.1.2 Accurate Representation 250S.1.3 Approximate Representation 251S.1.4 Representation of a Sequence 252S.2 The Spectrum Analyzer 253S.3 The Window Function 253S.4 Density and Discrete Spurs 254S.5 Control Parameters 255S.6 Frequency Conversion in an Analyzer 255S.7 Displaying L, FPSD, and PPSD 256S.8 Spectral Overlaps 256S.8.1 Aliasing 256S.8.2 Spectral Folding 257S.8.3 Image 258S.9 Anomalous Spurs 258Appendix T. Toolboxes 259Appendix U. Noise Produced By Charge Pump Current Unbalance (Mismatch) 261Appendix W. Getting Files From the Wiley Internet Site 265Appendix X. Some Tables 267X.1 Accumulator Shortening 267X.2 Sequence Lengths 268End Notes 269References 277Index 283

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