Frontiers in Electronic Testing

Data Mining and Diagnosing IC Fails

Fault Diagnosis of Analog Integrated Circuits

Advances in Electronic Testing

Challenges and Methodologies

Core Test Wrapper Handbook

Rationale and Application of IEEE Std. 1500™

Fault-Tolerance Techniques for SRAM-Based FPGAs

Digital Timing Measurements

From Scopes and Probes to Timing and Jitter

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Emerging Nanotechnologies

Test, Defect Tolerance, and Reliability

Boundary-Scan Interconnect Diagnosis

Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

On-Line Testing for VLSI

Formal Equivalence Checking and Design Debugging

Research Perspectives and Case Studies in System Test and Diagnosis

Delay Fault Testing for VLSI Circuits

Design for AT-Speed Test, Diagnosis and Measurement

Analog and Mixed-Signal Boundary-Scan

A Guide to the IEEE 1149.4 Test Standard

Testability Concepts for Digital ICs

The Macro Test Approach

Efficient Branch and Bound Search with Application to Computer-Aided Design

From Contamination to Defects, Faults and Yield Loss

Simulation and Applications

Multi-Chip Module Test Strategies

Reasoning in Boolean Networks

Logic Synthesis and Verification Using Testing Techniques

Introduction to IDDQ Testing

Embedded Processor-Based Self-Test

Introduction to Advanced System-on-Chip Test Design and Optimization

Oscillation-Based Test in Mixed-Signal Circuits

Designer’s Guide to Built-In Self-Test

Test Resource Partitioning for System-on-a-Chip

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

Power-Constrained Testing of VLSI Circuits

A Guide to the IEEE 1149.4 Test Standard