Delay Fault Testing for VLSI Circuits

With the ever-increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is further expected to grow with the late 20th-century design trend of moving towards deep submicron devices. After a long period of prevailing belief that high stuck-at fault coverage is sufficient to guarantee high quality of shipped products, the industry is now forced to rethink other types of testing. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed. Presenting a selection of existing delay testing research results, this volume combines introductory material with state-of-the-art techniques that address some of the problems in delay testing in the late 1990s. This text covers some basic topics such as fault modelling and test application schemes for detecting delay defects. It also presents summaries and conclusions of several recent case studies and experiments related to delay testing.A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. The book is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires a basic background in digital testing. It can also be used as supplementary material for a graduate-level course on VLSI testing.