Sigma-Delta Converters: Practical Design Guide

José M. de la Rosa is a Professor at the Institute of Microelectronics of Seville, IMSE-CNM (CSIC, University of Seville, Spain). His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance sigma-delta converters. He has worked in a number of international research and industrial projects and has co-authored over 200 peer-reviewed conference and journal papers dealing with sigma-delta ADCs. He served as Associated Editor of the IEEE Transactions on Circuits and Systems – I: Regular Papers, as Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems – II: Express Briefs, and as Distinguished Lecturer of the IEEE Circuits and Systems Society.

• Preface xixAcknowledgements xxvList of Abbreviations xxvii1 Introduction to 𝚺𝚫 Modulators: Fundamentals, Basic Architecture and Performance Metrics 11.1 Basics of Analog-to-Digital Conversion 21.1.1 Sampling 31.1.2 Quantization 41.1.3 Quantization White Noise Model 51.1.4 Noise Shaping 81.2 Sigma-Delta Modulation 91.2.1 From Noise-shaped Systems to ΣΔ Modulators 101.2.2 Performance Metrics of ΣΔMs 111.3 The First-order ΣΔ Modulator 131.4 Performance Enhancement and Taxonomy of ΣΔMs 161.4.1 ΣΔM System-level Design Parameters and Strategies 171.4.2 Classification of ΣΔMs 181.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs 191.5.1 Some Words about ΣΔ Decimators 201.6 ΣΔ DACs 221.6.1 System Design Trade-offs and Signal Processing in ΣΔ DACs 221.6.2 Implementation of Digital ΣΔMs used in DACs 241.7 Summary 25References 262 Taxonomy of 𝚺𝚫 Architectures 292.1 Second-order ΣΔ Modulators 302.1.1 Alternative Representations of Second-order ΣΔMs 312.1.2 Second-Order ΣΔM with Unity STF 342.2 High-order Single-loop ΣΔMs 352.3 Cascade ΣΔ Modulators 392.3.1 SMASH ΣΔM Architectures 462.4 Multi-bit ΣΔ Modulators 492.4.1 Influence of Multi-bit DAC Errors 492.4.2 Dynamic Element Matching Techniques 502.4.3 Dual Quantization 532.4.3.1 Dual-quantization Single-loop ΣΔMs 532.4.3.2 Dual-quantization Cascade ΣΔMs 542.5 Band-pass ΣΔ Modulators 552.5.1 Quadrature BP-ΣΔMs 562.5.2 The z → −z2 LP–BP Transformation 582.5.3 BP-ΣΔMs with Optimized NTF 582.5.4 Time-interleaved and Polyphase BP-ΣΔMs 612.6 Continuous-time ΣΔ Modulators: Architecture and Basic Concepts 642.6.1 An Intuitive Analysis of CT-ΣΔMs 662.6.2 Some Words about Alias Rejection in CT-ΣΔMs 692.7 DT–CT Transformation of ΣΔMs 702.7.1 The Impulse-invariant Transformation 702.7.2 DT–CT Transformation of a Second-order ΣΔM 722.8 Direct Synthesis of CT-ΣΔMs 742.9 Summary 76References 763 Circuit Errors in Switched-capacitor 𝚺𝚫 Modulators 833.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators 843.2 Finite Amplifier Gain in SC-ΣΔMs 863.3 Capacitor Mismatch in SC-ΣΔMs 903.4 Integrator Settling Error in SC-ΣΔMs 913.4.1 Behavioral Model for the Integrator Settling 913.4.2 Linear Effect of Finite Amplifier Gain–Bandwidth Product 953.4.3 Nonlinear Effect of Finite Amplifier Slew Rate 983.4.4 Effect of Finite Switch On-resistance 1003.5 Circuit Noise in SC-ΣΔMs 1013.6 Clock Jitter in SC-ΣΔMs 1053.7 Sources of Distortion in SC-ΣΔMs 1073.7.1 Nonlinear Amplifier Gain 1073.7.2 Nonlinear Switch On-Resistance 1093.8 Case Study: High-level Sizing of a ΣΔM 1113.8.1 Ideal Modulator Performance 1113.8.2 Noise Leakages 1123.8.3 Circuit Noise 1153.8.4 Settling Error 1163.8.5 Overall High-Level Sizing and Noise Budget 1173.9 Summary 119References 1194 Circuit Errors and Compensation Techniques in Continuous-time 𝚺𝚫 Modulators 1234.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators 1234.2 CT Integrators and Resonators 1244.3 Finite Amplifier Gain in CT-ΣΔMs 1264.4 Time-constant Error in CT-ΣΔMs 1284.5 Finite Integrator Dynamics in CT-ΣΔMs 1304.5.1 Effect of Finite Gain–Bandwidth Product on CT-ΣΔMs 1314.5.2 Effect of Finite Slew Rate on CT-ΣΔMs 1334.6 Sources of Distortion in CT-ΣΔMs 1344.6.1 Nonlinearities in the Front-end Integrator 1344.6.2 Intersymbol Interference in the Feedback DAC 1364.7 Circuit Noise in CT-ΣΔMs 1374.7.1 Noise Analysis Considering NRZ Feedback DACs 1374.7.2 Noise Analysis Considering SC Feedback DACs 1394.8 Clock Jitter in CT-ΣΔMs 1404.8.1 Jitter in Return-to-zero DACs 1414.8.2 Jitter in Non-return-to-zero DACs 1424.8.3 Jitter in Switched-capacitor DACs 1444.8.4 Lingering Effect of Clock Jitter Error 1454.8.5 Reducing the Effect of Clock Jitter with FIR and Sine-shaped DACs 1474.9 Excess Loop Delay in CT-ΣΔMs 1494.9.1 Intuitive Analysis of ELD 1494.9.2 Analysis of ELD based on Impulse-invariant DT-CT Transformation 1514.9.3 Alternative ELD Compensation Techniques 1544.10 Quantizer Metastability in CT-ΣΔMs 1554.11 Summary 159References 1605 Behavioral Modeling and High-level Simulation 1655.1 Systematic Design Methodology of ΣΔ Modulators 1655.1.1 System Partitioning and Abstraction Levels 1675.1.2 Sizing Process 1675.2 Simulation Approaches for the High-level Evaluation of ΣΔMs 1695.2.1 Alternatives to Transistor-level Simulation 1695.2.2 Event-driven Behavioral Simulation Technique 1715.2.3 Programming Languages and Behavioral Modeling Platforms 1725.3 Implementing ΣΔM Behavioral Models 1735.3.1 From Circuit Analysis to Computational Algorithms 1735.3.2 Time-domain versus Frequency-domain Behavioral Models 1755.3.3 Implementing Time-domain Behavioral Models in MATLAB 1785.3.4 Building Time-domain Behavioral Models as SIMULINK C-MEX S-functions 1825.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-functions 1885.4.1 Modeling of SC Integrators using S-functions 1885.4.1.1 Capacitor Mismatch and Nonlinearity 1905.4.1.2 Input-referred Thermal Noise 1915.4.1.3 Switch On-resistance Dynamics 1945.4.1.4 Incomplete Settling Error 1975.4.2 Modeling of CT Integrators using S-functions 2005.4.2.1 Single-pole Gm-C Model 2005.4.2.2 Two-pole Dynamics Model 2015.4.2.3 Modeling Transconductors as S-functions 2035.4.3 Behavioral Modeling of Quantizers using S-functions 2055.4.3.1 Modeling Multi-level ADCs as S-functions 2055.4.3.2 Modeling Multi-level DACs as S-functions 2075.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs 2095.5.1 Model Libraries Included in SIMSIDES 2105.5.2 Structure of SIMSIDES and its User Interface 2115.5.2.1 Creating a New ΣΔM Block Diagram 2125.5.2.2 Setting Model Parameters 2155.5.2.3 Simulation Analyses 2155.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs 2165.6.1 SC Second-order Single-Bit ΣΔM 2165.6.1.1 Effect of Amplifier Finite DC Gain 2185.6.1.2 Effect of Thermal Noise 2185.6.1.3 Effect of the Incomplete Settling Error 2205.6.1.4 Cumulative Effect of All Errors 2215.6.2 CT Fifth-order Cascade 3-2 Multi-bit ΣΔM 2245.6.2.1 Effect of Nonideal Effects 2275.6.2.2 High-level Synthesis and Verification 2295.7 Summary 231References 2316 Automated Design and Optimization of 𝚺𝚫Ms 2356.1 Architecture Exploration and Selection: Schreier’s Toolbox 2366.1.1 Basic Functions of Schreier’s Delta-Sigma Toolbox 2366.1.2 Synthesis of a Fourth-order CRFF LP/BP SC-ΣΔM with Tunable Notch 2386.1.3 Synthesis of a Fourth-order BP CT-ΣΔM with Tunable Notch 2406.2 Optimization-based High-level Synthesis of ΣΔ Modulators 2456.2.1 Combining Behavioral Simulation and Optimization 2466.2.2 Using Simulated Annealing as Optimization Engine 2476.2.3 Combining SIMSIDES with MATLAB Optimizers 2536.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs 2556.3.1 Hardware Emulation of CT-ΣΔMs on an FPGA 2576.3.2 GPU-accelerated Computing of CT-ΣΔMs 2586.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs 2596.4.1 Combining MOEA with SIMSIDES 2616.4.2 Applying MOEA and SIMSIDES to the Synthesis of CT-ΣΔMs 2626.5 Summary 269References 2697 Electrical Design of 𝚺𝚫Ms: From Systems to Circuits 2717.1 Macromodeling ΣΔMs 2727.1.1 SC Integrator Macromodel 2727.1.1.1 Switch Macromodel 2727.1.1.2 OTA Macromodel 2747.1.2 CT Integrator Macromodel 2747.1.2.1 Active-RC Integrators 2747.1.2.2 Gm-C Integrators 2747.1.3 Nonlinear OTA Transconductor 2757.1.4 Embedded Flash ADC Macromodel 2767.1.5 Feedback DAC Macromodel 2777.2 Examples of ΣΔM Macromodels 2797.2.1 SC Second-order Example 2797.2.2 Second-order Active-RC ΣΔM 2837.3 Including Noise in Transient Electrical Simulations of ΣΔMs 2867.3.1 Generating and Injecting Noise Data Sequences in HSPICE 2877.3.2 Analyzing the Impact of the Main Noise Sources in SC Integrators 2897.3.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations 2897.3.4 Test Bench to Include Noise in the Simulation of ΣΔMs 2937.4 Processing ΣΔM Output Results of Electrical Simulations 2947.5 Summary 298References 2988 Design Considerations of 𝚺𝚫M Subcircuits 3018.1 Design Considerations of CMOS Switches 3028.1.1 Trade-Off Between Ron and the CMOS Switch Drain/Source Parasitic Capacitances 3028.1.2 Characterizing the Nonlinear Behavior of Ron 3028.1.3 Influence of Technology Downscaling on the Design of Switches 3048.1.4 Evaluating Harmonic Distortion due to CMOS Switches 3058.2 Design Considerations of Operational Amplifiers 3088.2.1 Typical Amplifier Topologies 3098.2.2 Common-mode Feedback Networks 3118.2.3 Characterization of the Amplifier in AC 3138.2.4 Characterization of the Amplifier in DC 3138.2.5 Characterization of the Amplifier Gain Nonlinearity 3168.3 Design Considerations of Transconductors 3178.3.1 Highly Linear Front-end Transconductor 3188.3.2 Loop-filter Transconductors 3208.3.3 Widely Programmable Transconductors 3238.4 Design Considerations of Comparators 3248.4.1 Regenerative Latch-based Comparators 3258.4.2 Design Guidelines of Comparators 3278.4.3 Characterization of Offset and Hysteresis Based on the Input-ramp Method 3288.4.4 Characterization of Offset and Hysteresis Based on the Bisectional Method 3288.4.5 Characterizing the Comparison Time 3308.5 Design Considerations of Current-Steering DACs 3328.5.1 Fundamentals and Basic Concepts of CS DACs 3338.5.2 Practical Realization of CS DACs 3338.5.3 Current Cell Circuits, Error Limitations, and Design Criteria 3368.5.4 CS 4-bit DAC Example 3368.6 Summary 338References 3389 Practical Realization of 𝚺𝚫Ms: From Circuits to Chips 3419.1 Auxiliary ΣΔM Building Blocks 3419.1.1 Clock-phase Generators 3429.1.1.1 Phase Generation 3429.1.1.2 Phase Buffering 3429.1.1.3 Phase Distribution 3449.1.2 Generation of Common-mode Voltage, Reference Voltage, and Bias Currents 3459.1.2.1 Bandgap Circuit 3459.1.2.2 Reference Voltage Generator 3459.1.2.3 Master Bias Current Generator 3469.1.2.4 Common-mode Voltage Generator 3469.1.3 Additional Digital Logic 3479.2 Layout Design, Floorplanning, and Practical Issues 3489.2.1 Layout Floorplanning 3489.2.1.1 Divide Layout into Different Parts or Regions 3489.2.1.2 Shield Sensitive ΣΔM Analog Subcircuits from Switching Noise 3499.2.1.3 Buses to Distribute Signals Shared by Different ΣΔM Parts 3499.2.1.4 Be Obsessive about Layout Symmetry and Details of Analog Parts 3499.2.2 I/O Pad Ring 3509.2.3 Importance of Layout Verification and Catastrophic Failure 3509.3 Chip Package, Test PCB, and Experimental Setup 3549.3.1 Bonding Diagram and Package 3549.3.2 Test PCB 3559.4 Experimental Test Set-Up 3559.4.1 Planning the Type and Number of Instruments Needed 3579.4.2 Connecting Lab Instruments 3579.4.3 Measurement Set-Up Example 3589.5 ΣΔM Design Examples and Case Studies 3599.5.1 Programmable-gain ΣΔMs for High Dynamic Range Sensor Interfaces 3609.5.1.1 Main Design Criteria and Performance Limitations 3619.5.1.2 SC Realization with Programmable Gain and Double Sampling 3629.5.1.3 Influence of Chopper Frequency on Flicker Noise 3629.5.2 Reconfigurable SC-ΣΔMs for Multi-standard Direct Conversion Receivers 3649.5.2.1 Power-scaling Circuit Techniques 3679.5.2.2 Experimental Results 3689.5.3 Using Widely-programmable Gm-LC BP-ΣΔMs for RF Digitizers 3689.5.3.1 Application Scenario 3719.5.3.2 Gm-LC BP-ΣΔM High-level Sizing 3719.5.3.3 BP CT-ΣΔM Loop-Filter Reconfiguration Techniques 3759.5.3.4 Embedded 4-bit Quantizer with Calibration 3789.5.3.5 Biasing, Digital Control Programmability and Testability 3829.6 Summary 385References 38610 Frontiers, Trends and Challenges: Towards Next-generation 𝚺𝚫 Modulators 38910.1 State-of-the-Art ADCs: Nyquist-rate versus ΣΔ Converters 39010.1.1 Conversion Energy 39110.1.2 Figures of Merit 39210.2 Comparison of Different Categories of ΣΔ ADCs 39310.2.1 Aperture Plot of ΣΔMs 40610.2.2 Energy Plot of ΣΔMs 40710.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 40810.3.1 SC versus CT ΣΔMs 40810.3.2 Technology used in State-of-the-Art ΣΔMs 41010.3.3 Single-Loop versus Cascade ΣΔMs 41010.3.4 Single-bit versus Multi-bit ΣΔMs 41110.3.5 Low-pass versus Band-pass ΣΔMs 41310.3.6 Emerging ΣΔM Techniques 41510.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion 41510.5 Enhanced Cascade ΣΔMs 41810.5.1 SMASH CT-ΣΔMs 41810.5.2 Two-stage 0-L MASH 41910.5.3 Stage-sharing Cascade ΣΔMs 42010.5.4 Multi-rate and Hybrid CT/DT ΣΔMs 42010.5.4.1 Upsampling Cascade MR-ΣΔMs 42110.5.4.2 Downsampling Hybrid CT/DT Cascade MR-ΣΔMs 42210.6 Power-efficient ΣΔM Loop-filter Techniques 42310.6.1 Inverter-based ΣΔMs 42310.6.2 Hybrid Active/Passive and Amplifier-less ΣΔMs 42410.6.3 Power-efficient Amplifier Techniques 42610.7 Hybrid ΣΔM/Nyquist-rate ADCs 42810.7.1 Multi-bit ΣΔM Quantizers based on Nyquist-rate ADCs 42810.7.2 Incremental ΣΔ ADCs 42910.8 Time-based ΣΔ ADCs 43110.8.1 ΣΔMs with VCO/PWM-based Quantization 43210.8.2 Scaling-friendly Mostly-digital ΣΔMs 43310.8.3 GRO-based ΣΔMs 43410.9 DAC Techniques for High-performance CT-ΣΔMs 43610.10 Classification of State-of-the-Art References 43710.11 Summary and Conclusions 437References 438A State-space Analysis of Clock Jitter in CT-𝚺𝚫Ms 463A.1 State-space Representation of NTF (z) 463A.2 Expectation Value of (Δqn)2 465A.3 In-band Noise Power due to Clock Jitter 466References 467B SIMSIDES User Guide 469B.1 Getting Started: Installing and Running SIMSIDES 470B.2 Building and Editing ΣΔM Architectures in SIMSIDES 470B.3 Analyzing ΣΔMs in SIMSIDES 473B.3.1 Node Spectrum Analysis 474B.3.2 Integrated Power Noise 474B.3.3 SNR/SNDR 475B.3.4 Harmonic Distortion 475B.3.5 Integral and Differential Non-Linearity 477B.3.6 Multi-tone Power Ratio 477B.3.7 Histogram 478B.3.8 Parametric Analysis 478B.3.9 Monte Carlo Analysis 479B.4 Optimization Interface 480B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs 482B.5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES 482B.5.2 Setting Model Parameters 482B.5.3 Computing the Output Spectrum 484B.5.4 SNR versus Input Amplitude Level 486B.5.5 Parametric Analysis Considering Only One Parameter 487B.5.6 Parametric Analysis Considering Two Parameters 488B.5.7 Computing Histograms 489B.6 Getting Help 489C SIMSIDES Block Libraries and Models 491C.1 Overview of SIMSIDES Libraries 491C.2 Ideal Libraries 492C.2.1 Ideal Integrators 492C.2.1.1 Building-block Model Purpose and Description 492C.2.1.2 Model Parameters 493C.2.2 Ideal Resonators 493C.2.2.1 Ideal_LD_Resonator 493C.2.2.2 Ideal_FE_Resonator 493C.2.2.3 Ideal_CT_Resonator 493C.2.3 Ideal Quantizers 494C.2.3.1 Ideal_Comparator 494C.2.3.2 Ideal_Comparator_for_SI 495C.2.3.3 Ideal_Multibit_Quantizer 495C.2.3.4 Ideal_Multibit_Quantizer_for_SI 496C.2.3.5 Ideal_Multibit_Quantizer_levels 496C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 496C.2.3.7 Ideal_Sampler 496C.2.4 Ideal D/A Converters 496C.2.4.1 Ideal_DAC_for_SI 496C.2.4.2 Ideal_DAC_dig_level_SD2 497C.3 Real SC Building-Block Libraries 497C.3.1 Real SC Integrators 497C.3.2 Real SC Resonators 501C.4 Real SI Building-Block Libraries 503C.4.1 Real SI Integrators 503C.4.2 Real SI Resonators 505C.4.3 SI Errors and Model Parameters 506C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator 506C.4.3.2 SI_FE(LD)_Int_Finite_Conductance 507C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection 508C.5 Real CT Building-Block Libraries 508C.5.1 Real CT Integrators 508C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks 511C.5.1.2 Gm-MC Integrators 511C.5.1.3 Active-RC Integrators 512C.5.1.4 MOSFET-C Integrators 513C.5.2 Real CT Resonators 513C.5.2.1 Gm-C Resonators 514C.5.2.2 Gm-LC Resonators 517C.6 Real Quantizers & Comparators 517C.7 Real D/A Converters 518C.8 Auxiliary Blocks 519Index 523