Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. (2) an RTL error diagnosis method that identifies the root cause of errors directly;
Winner of the EDAA (European Design Automation Association) Outstanding Monograph Award in the Verification section. Co-authors Bertacco and Markov are existing Springer authors
Background and Prior Art.- Current Landscape in Design and Verification.- Finding Bugs and Repairing Circuits.- FogClear Methodologies and Theoretical Advances in Error Repair.- Circuit Design and Verification Methodologies.- Counterexample-Guided Error-Repair Framework.- Signature-Based Resynthesis Techniques.- Symmetry-Based Rewiring.- FogClear Components.- Bug Trace Minimization.- Functional Error Diagnosis and Correction.- Incremental Verification for Physical Synthesis.- Post-Silicon Debugging and Layout Repair.- Methodologies for Spare-Cell Insertion.- Conclusions.
Luciano Lavagno, Grant E. Martin, Igor L. Markov, Louis K. Scheffer, Italy) Lavagno, Luciano (Politecnico di Torino, USA) Markov, Igor L. (University of Michigan, Ann Arbor, USA) Martin, Grant (Cadence Design Systems, Inc., San Jose, California, USA) Scheffer, Louis K. (Howard Hughes Medical Institute, Ashburn, Virginia
Luciano Lavagno, Grant Martin, Igor L. Markov, Louis K. Scheffer, Italy) Lavagno, Luciano (Politecnico di Torino, USA) Markov, Igor L. (University of Michigan, Ann Arbor, USA) Martin, Grant (Cadence Design Systems, Inc., San Jose, California, USA) Scheffer, Louis K. (Howard Hughes Medical Institute, Ashburn, Virginia