FPGA Prototyping by SystemVerilog Examples

PONG P. CHU, PhD is an Associate Professor in the Department of Electrical Engineering and Computer Science at Cleveland State University, Cleveland, Ohio. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and has received multiple instructional grants from the National Science Foundation.

• Preface xxviiAcknowledgments xxxiiiPART I BASIC DIGITAL CIRCUITS DEVELOPMENT1 Gate-Level Combinational Circuit 11.1 Introduction 11.1.1 Brief history of Verilog and SystemVerilog 11.1.2 Book coverage 21.2 General description 31.3 Basic lexical elements and data types 41.3.1 Lexical elements 41.3.2 Data types used in the book 51.3.3 Number representation 61.3.4 Operators 71.4 Program skeleton 71.4.1 Port declaration 71.4.2 Signal declaration 81.4.3 Program body 81.4.4 Concurrent semantics 91.4.5 Another example 101.5 Structural description 101.6 Top-level signal mapping 131.7 Testbench 141.8 Bibliographic notes 161.9 Suggested experiments 161.9.1 Code for gate-level greater-than circuit 171.9.2 Code for gate-level binary decoder 172 Overview of FPGA and EDA Software 192.1 FPGA 192.1.1 Overview of a general FPGA device 192.1.2 Overview of the Xilinx Artix-7 devices 202.2 Overview of the Digilent Nexys 4 DDR board 212.3 Development flow 222.4 Xilinx Vivado Design Suite 242.5 Bibliographic notes 242.6 Suggested experiments 242.6.1 Gate-level greater-than circuit 242.6.2 Gate-level binary decoder 263 RT-Level Combinational Circuit 293.1 Operators 293.1.1 Arithmetic operators 313.1.2 Shift operators 313.1.3 Relational and equality operators 323.1.4 Bitwise, reduction, and logical operators 323.1.5 Concatenation and replication operators 333.1.6 Conditional operators 343.1.7 Operator precedence 353.1.8 Expression bit-length adjustment 353.1.9 Synthesis of z and x values 363.2 Always block for a combinational circuit 383.2.1 Overview of always block 393.2.2 Procedural assignment 403.2.3 Conceptual examples 403.3 Coding guidelines 433.4 If statement 433.4.1 Syntax 433.4.2 Examples 443.5 Case statement 453.5.1 Syntax 453.5.2 Examples 463.5.3 The casez and casex statements 473.5.4 Full case and parallel case 483.6 Routing structure of conditional control constructs 493.6.1 Priority routing network 493.6.2 Multiplexing network 513.7 Additional coding guidelines for an always block 523.7.1 Common errors in combinational circuit codes 523.7.2 Guidelines 563.8 Parameter and constant 563.8.1 Constant 563.8.2 Parameter 583.9 Replicated structure 593.9.1 Generate-for statement 593.9.2 Procedural-for statement 603.9.3 Example 603.10 Design examples 623.10.1 Hexadecimal digit to seven-segment LED decoder 623.10.2 Sign-magnitude adder 653.10.3 Barrel shifter 683.10.4 Simplified floating-point adder 693.11 Bibliographic notes 733.12 Suggested experiments 733.12.1 Multi-function barrel shifter 733.12.2 Parameterized barrel shifter 743.12.3 Dual-priority encoder 743.12.4 BCD incrementor 743.12.5 Floating-point greater-than circuit 743.12.6 Floating-point and signed integer conversion circuit 743.12.7 Enhanced floating-point adder 754 Regular Sequential Circuit 774.1 Introduction 774.1.1 D FF and register 784.1.2 Basic block system 784.1.3 Code development 794.1.4 Sequential circuit coding guidelines and style 794.2 HDL code of the FF and register 804.2.1 D FF 804.2.2 Register 854.3 Simple design examples 854.3.1 Shift register 854.3.2 Binary counter and variant 874.4 Testbench for sequential circuits 894.5 Case study 934.5.1 LED time-multiplexing circuit 934.5.2 Stopwatch 1014.6 Timing and clocking 1044.6.1 Timing of FF 1044.6.2 Maximum operating frequency 1044.6.3 Clock tree 1074.6.4 GALS system and CDC 1074.7 Bibliographic notes 1084.8 Suggested experiments 1084.8.1 Programmable square wave generator 1084.8.2 PWM and LED dimmer 1084.8.3 Rotating square circuit 1094.8.4 Heartbeat circuit 1094.8.5 Rotating LED banner circuit 1094.8.6 Enhanced stopwatch 1105 FSM 1115.1 Introduction 1115.1.1 Mealy and Moore outputs 1125.1.2 FSM representation 1125.2 FSM code development 1155.2.1 Enumerated data type and state assignment 1155.2.2 Multi-segment code 1165.2.3 Two-segment code 1175.3 Design examples 1185.3.1 Rising-edge detector 1185.3.2 Debouncing circuit 1235.3.3 Testing circuit 1265.4 Bibliographic notes 1285.5 Suggested experiments 1285.5.1 Dual-edge detector 1285.5.2 Early detection debouncing circuit 1285.5.3 Parking lot occupancy counter 1296 FSMD 1316.1 Introduction 1316.1.1 Single RT operation 1326.1.2 ASMD chart 1326.1.3 Decision box with a register 1346.2 Code development of an FSMD 1376.2.1 Debouncing circuit based on RT methodology 1376.2.2 Code with explicit data path components 1376.2.3 Code with implicit data path components 1406.2.4 Comparison 1426.3 Design examples 1446.3.1 Fibonacci number circuit 1446.3.2 Division circuit 1476.3.3 Binary-to-BCD conversion circuit 1506.3.4 Period counter 1536.3.5 Accurate low-frequency counter 1566.4 Bibliographic notes 1596.5 Suggested experiments 1596.5.1 Early detection debouncing circuit 1596.5.2 BCD-to-binary conversion circuit 1606.5.3 Fibonacci circuit with BCD I/O: design approach 1 1606.5.4 Fibonacci circuit with BCD I/O: design approach 2 1606.5.5 Auto-scaled low-frequency counter 1616.5.6 Reaction timer 1616.5.7 Babbage difference engine emulation circuit 1627 RAM and Buffer of FPGA 1657.1 Embedded memory of FPGA device 1657.1.1 Memory of an Artix device 1667.1.2 Memory available in the Nexys 4 DDR board 1667.2 General description for a RAM-like component 1677.2.1 Register file 1677.2.2 Dynamic array indexing operation 1697.2.3 Key aspects of a RAM module 1707.2.4 Genuine ROM 1717.3 FIFO buffer 1737.3.1 FIFO read configuration 1747.3.2 Circular queue implementation 1757.4 HDL templates for memory inference 1787.4.1 Methods to incorporate memory modules 1787.4.2 Synchronous dual-port RAM 1797.4.3 “Simple” synchronous dual-port RAM 1807.4.4 Synchronous single-port RAM 1817.4.5 Synchronous ROM 1827.4.6 BRAM-based FIFO buffer 1837.4.7 Design considerations 1837.5 Overview of memory controller 1847.6 Bibliographic notes 1857.7 Suggested experiments 1867.7.1 ROM-based sign-magnitude adder 1867.7.2 ROM-based temperature conversion 1867.7.3 FIFO with data width conversion 1867.7.4 Standard FIFO to FWFT FIFO conversion circuit 1877.7.5 FIFO buffer with extended status 1877.7.6 Stack 1878 Selected Topics of SystemVerilog 1898.1 Timing model 1898.1.1 Concurrent constructs 1908.1.2 Assignment statement 1908.1.3 Basic model 1908.1.4 Blocking versus nonblocking assignment 1928.2 Coding guidelines revisited 1948.2.1 “Single variable assignment” guideline 1958.2.2 “Blocking assignment for combinational circuit” guideline 1958.2.3 “Nonblocking assignment for register” guideline 1978.3 Alternative coding style 1988.3.1 First coding style revisited 1988.3.2 Sequential circuit with mixed blocking and nonblocking assignments 1998.3.3 Combined coding style 2018.3.4 Summary 2068.4 Data types 2068.4.1 The net and variable types 2068.4.2 The logic data type 2078.4.3 Limitation of the logic data type 2088.4.4 New data types in SystemVerilog 2088.5 Use of the signed data type 2098.5.1 Overview 2098.5.2 Signed number conversion 2108.6 Bibliographic notes 2118.7 Suggested experiments 2118.7.1 Shift register with blocking and nonblocking assignments 2118.7.2 Alternative coding style for the BCD counter 2128.7.3 Alternative coding style for the FIFO buffer 2128.7.4 Alternative coding style for the Fibonacci circuit 2128.7.5 Dual-mode comparator 212PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM9 Overview of Embedded SoC Systems 2159.1 Embedded SoC 2159.1.1 Overview of embedded systems 2159.1.2 FPGA-based SoC 2169.1.3 IP cores 2169.2 Development flow of the embedded SoC 2179.2.1 Hardware–software partition 2179.2.2 Hardware development flow 2179.2.3 Software development flow 2199.2.4 Physical implementation and test 2199.2.5 Custom IP core development 2199.3 FPro SoC Platform 2209.3.1 Motivations 2209.3.2 Platform hardware organization 2219.3.3 Platform software organization 2239.3.4 Modified development flow 2249.4 Adaptation on the Digilent Nexys 4 DDR board 2249.5 Portability 2269.5.1 Processor Module and Bridge 2269.5.2 MMIO subsystem 2279.5.3 Video subsystem 2279.6 Organization 2289.7 Bibliographic notes 22810 Bare Metal System Software Development 23110.1 Bare metal system development overview 23110.1.1 Desktop-like system versus bare metal system 23110.1.2 Basic embedded program architecture 23210.2 Memory-mapped I/O 23310.2.1 Overview 23310.2.2 Memory alignment 23410.2.3 I/O register map 23410.2.4 I/O address space of the FPro system 23410.3 Direct I/O Register Access 23510.3.1 Review of C pointer 23510.3.2 C pointer for I/O register 23610.4 Robust I/O register access 23710.4.1 chu_io_map.h and chu_io_map.svh 23710.4.2 inttypes.h 23810.4.3 chu_io_rw.h 23910.5 Techniques for low-level I/O operations 24110.5.1 Bit manipulation 24110.5.2 Packing and unpacking 24210.6 Device Drivers 24310.6.1 Overview 24310.6.2 GPO and GPI drivers 24310.6.3 Timer driver 24510.6.4 UART driver 24710.7 FPro utility routines and directory structure 24810.7.1 Minimal hardware requirements 24810.7.2 Utility routines 24810.7.3 Directory structure 25110.8 Test program 25210.8.1 IP core verification routine 25210.8.2 Programming with limited memory 25210.8.3 Test function integration 25210.8.4 Test program for the vanilla FPro system 25310.8.5 Implementation 25410.9 Bibliographic notes 25510.10 Suggested experiments 25510.10.1 Chasing LEDs 25510.10.2 Collision LEDs 25610.10.3 Pulse width modulation 25610.10.4 System time display 25611 FPro Bus Protocol and MMIO Slot Specification 25711.1 FPro bus 25711.1.1 Overview of the bus 25711.1.2 SoC interconnect 25811.1.3 FPro bus protocol specification 25911.2 Interface with the bus 26011.2.1 Introduction 26011.2.2 Write interface and decoding 26111.2.3 Read interface and multiplexing 26311.2.4 FIFO buffer as an I/O register 26411.2.5 Timing consideration 26511.3 MMIO I/O core 26611.3.1 MMIO slot interface specification 26611.3.2 Basic MMIO I/O core construction 26811.3.3 GPO and GPI cores 26911.4 Timer core development 27011.4.1 Custom logic 27011.4.2 Register map 27111.4.3 Wrapping circuit for the slot interface 27111.5 MMIO controller 27211.5.1 chu_io_map.svh file 27311.5.2 HDL code 27311.5.3 Vanilla MMIO subsystem 27511.6 MCS I/O bus and bridge 27811.6.1 Overview of Xilinx MicroBlaze MCS 27811.6.2 MicroBlaze MCS I/O bus 27811.6.3 MCS-to-FPro bridge 27911.7 Vanilla FPro system construction 28111.8 Bibliographic notes 28211.9 Suggested experiments 28311.9.1 FPro bus with a byte-lane enable signal 28311.9.2 Seven-segment control with a GPO core 28311.9.3 GPIO core 28311.9.4 Blinking-LED core 28411.9.5 Timer core with a programmable period 28411.9.6 Timer core with a run-once mode 28412 UART Core 28712.1 Introduction 28712.1.1 Overview of serial communication 28712.1.2 Overview of the UART 28812.1.3 Oversampling procedure 28812.2 UART construction 28912.2.1 Conceptual design 28912.2.2 Baud rate generator 29012.2.3 UART receiver 29112.2.4 UART transmitter 29312.2.5 Top-level HDL code 29512.3 UART core development 29612.3.1 Register map 29612.3.2 Wrapping circuit for the slot interface 29712.4 UART driver 29812.4.1 Class definition 29912.4.2 Basic methods 30012.4.3 ASCII code 30112.4.4 Display methods 30312.4.5 Test 30512.5 Additional project ideas 30512.5.1 Original serial port 30512.5.2 Emulated serial port 30512.5.3 Direct connection 30612.5.4 USB-to-UART adaptor 30612.5.5 Wireless adaptor 30712.6 Bibliographic notes 30812.7 Suggested experiments 30812.7.1 UART-controlled chasing LEDs 30812.7.2 Alternative read configuration 30812.7.3 UART controller with a parity bit 30812.7.4 UART core with an error status 30912.7.5 Configurable UART core 30912.7.6 UART core with automatic baud rate detection 30912.7.7 UART core with enhanced automatic baud rate detection 31012.7.8 UART core with an automatic baud rate and a parity detection circuit 310PART III EMBEDDED SOC II: BASIC I/O CORES13 Xilinx XADC Core 31313.1 Overview of XADC 31313.1.1 Block diagram 31313.1.2 Configuration 31413.2 XADC core development 31513.2.1 XADC instantiation 31513.2.2 Basic wrapping circuit design 31613.2.3 Register map 31813.2.4 HDL code 31813.3 XADC core device driver 32013.3.1 Class definition 32013.3.2 Class implementation 32113.3.3 Testing for the XADC core 32213.4 Sampler FPro system 32313.4.1 Testing procedure of an FPro core 32313.4.2 System configuration 32313.4.3 Hardware derivation 32413.4.4 Software verification program 33113.5 Additional project ideas 33213.6 Bibliographic notes 33313.7 Suggested experiments 33313.7.1 Real-time voltage display 33313.7.2 Potentiometer-controlled chasing LEDs 33313.7.3 Potentiometer-controlled LED dimmer 33313.7.4 Enhanced wrapping circuit: part I 33313.7.5 Enhanced wrapping circuit: part II 33314 Pulse Width Modulation Core 33514.1 Introduction 33514.1.1 PWM as analog output 33514.1.2 Main characteristics 33614.2 PWM design 33614.2.1 Basic design 33614.2.2 Enhanced design 33714.3 PWM core development 33914.3.1 Register map 33914.3.2 Wrapped PWM circuit 34014.4 PWM driver 34114.4.1 Class definition 34114.4.2 Class implementation 34214.5 Testing 34314.6 Project ideas 34314.7 Suggested experiments 34514.7.1 Police dash light 34514.7.2 Rainbow night light 34514.7.3 Enhanced PWM core: part I 34514.7.4 Enhanced PWM core: part II 34614.7.5 Enhanced GPIO core 34614.7.6 Servo motor driver 34615 Debouncing Core and LED-Mux Core 34715.1 Debouncing Core 34715.1.1 Multi-bit debouncing circuit 34715.1.2 Register map and the slot wrapping circuit 35015.1.3 Driver 35115.1.4 Test 35215.2 LED-mux core 35215.2.1 Eight-digit seven-segment LED display multiplexing circuit 35215.2.2 Register map and the slot wrapping circuit 35415.2.3 Driver 35515.2.4 Test 35815.3 Project ideas 35815.4 Suggested experiments 36015.4.1 Area comparison of two debouncing circuits 36015.4.2 Enhanced debouncing core: part I 36015.4.3 Enhanced debouncing core: part II 36015.4.4 Rotating square pattern revisited 36015.4.5 Heartbeat pattern revisited 36015.4.6 Stopwatch 36015.4.7 Enhanced LED-mux core 36116 SPI Core 36316.1 Overview 36316.1.1 Conceptual architecture 36416.1.2 Multiple-device configuration 36416.1.3 Basic timing 36616.1.4 Operation modes 36716.1.5 Undefined aspects 36816.2 SPI controller 36916.2.1 Basic design 36916.2.2 FSMD construction 37016.2.3 HDL implementation 37016.3 SPI core development 37416.3.1 Register map 37416.3.2 Wrapping circuit for the slot interface 37416.4 SPI driver 37616.4.1 Class definition 37616.4.2 Class implementation 37716.5 Test 37816.5.1 ADXL362 accelerometer 37816.5.2 Test program 38016.6 Project ideas 38116.6.1 SD card 38116.6.2 TFT LCD module 38216.7 Bibliographic notes 38216.8 Suggested experiments 38216.8.1 Inclination sensing 38216.8.2 “Tapping” detection 38216.8.3 ADXL362 C++ class 38316.8.4 Enhanced SPI controller: part I 38316.8.5 Enhanced SPI controller: part II 38316.8.6 “Automatic-read” ADXL362 wrapper: part I 38316.8.7 “Automatic-read” ADXL362 wrapper: part II 38416.8.8 Flash memory access 38416.8.9 SPI slave controller: part I 38416.8.10 SPI slave controller: part II 38517 I2C Core 38717.1 Overview 38717.1.1 Electrical characteristics 38817.1.2 Basic bus protocol 38817.1.3 Basic timing 38917.1.4 Additional features 39017.2 I2C controller 39117.2.1 Basic design 39117.2.2 Conceptual FSMD construction 39117.2.3 Output control logic 39417.2.4 I2C bus clock generation 39417.2.5 HDL implementation 39517.3 I2C core development 40017.3.1 Register map 40017.3.2 Wrapping circuit for the slot interface 40017.4 I2C driver 40117.4.1 Class definition 40117.4.2 Class implementation 40217.5 Test 40517.5.1 ADT7420 temperature sensor 40517.5.2 Test program 40617.6 Project idea 40617.7 Bibliographic notes 40717.8 Suggested experiments 40717.8.1 Thermometer 40717.8.2 ADT7420 C++ class 40717.8.3 Enhanced I2C core 40817.8.4 “Automatic-read” ADT7420 wrapper 40817.8.5 I2C slave controller: part I 40817.8.6 I2C slave controller: part II 40818 PS2 Core 40918.1 Introduction 40918.1.1 PS2-device-to-host communication protocol and timing 41018.1.2 Host-to-PS2-device communication protocol and timing 41018.2 PS2 controller 41118.2.1 Conceptual design 41118.2.2 PS2 receiving subsystem 41118.2.3 PS2 transmitting subsystem 41518.2.4 Complete PS2 system 41918.3 PS2 core development 42018.3.1 Register map 42018.3.2 Wrapping circuit for the slot interface 42118.4 PS2 driver 42218.4.1 Class definition 42218.4.2 Lower layer methods 42218.4.3 PS2 initialization routine 42318.4.4 Keyboard routine 42518.4.5 Mouse routine 42818.5 Test 43018.6 Bibliographic notes 43118.7 Suggested experiments 43118.7.1 PS2 receiving subsystem with watchdog timer 43118.7.2 Keyboard-controlled LED flashing circuit 43218.7.3 Enhanced keyboard driver routine: part I 43218.7.4 Enhanced keyboard driver routine: part II 43218.7.5 Remote-mode mouse driver 43218.7.6 Scroll-wheel mouse driver 43219 Sound I: DDFS Core 43319.1 Introduction 43319.2 Design and implementation 43419.2.1 Direct synthesis of a digital waveform 43419.2.2 Direct synthesis of an unmodulated analog waveform 43519.2.3 Direct synthesis of a modulated analog waveform 43619.3 Fixed-point arithmetic 43719.4 DDFS construction 43819.5 DAC (digital-to-analog converter) 44019.5.1 Conceptual design 44019.5.2 HDL implementation 44119.6 DDFS core development 44219.6.1 Register map 44219.6.2 Wrapping circuit for the slot interface 44319.7 DDFS driver 44419.7.1 Class definition 44419.7.2 Class implementation 44519.8 Test 44719.9 Bibliographic notes 44819.10 Suggested experiments 44819.10.1 Quadrature phase carrier generation 44819.10.2 Reduced-size phase-to-amplitude lookup table 44819.10.3 Additive harmonic synthesis 44919.10.4 Simple function generator 44919.10.5 Arbitrary waveform generator 44919.10.6 Sample-based synthesis 44920 Sound II: ADSR Core 45120.1 Introduction 45120.2 ADSR envelope generator 45220.2.1 Conceptual FSMD design 45320.2.2 ASMD chart 45320.2.3 HDL implementation 45520.3 ADSR core development 45720.3.1 Register map 45720.3.2 Wrapped ADSR circuit 45820.4 ADSR driver 46020.4.1 Class definition 46020.4.2 Configuration methods 46120.4.3 calc note freq() method 46320.4.4 play note() method 46520.5 Test 46520.6 Project idea 46620.7 Bibliographic notes 46720.8 Suggested experiments 46720.8.1 RTTTL music player 46720.8.2 ADSR envelope testing 46720.8.3 Pushbutton piano 46720.8.4 Keyboard piano 46820.8.5 Keyboard recorder 46820.8.6 Real-time mode ADSR generator 46820.8.7 Real-time mode pushbutton piano 46820.8.8 Merged DDFS and ADSR core 46820.8.9 ADSR core with an automatic play FIFO buffer 46820.8.10 ADSR core for frequency modulation 468PART IV EMBEDDED SOC III: VIDEO CORES21 Introduction to the Video System 47121.1 Introduction to a video display 47121.1.1 Conceptual video display 47121.1.2 VGA interface 47221.2 Stream interface 47321.2.1 Random-access interface versus stream interface 47321.2.2 Flow control of the stream interface 47321.3 VGA synchronization 47521.3.1 Basic operation of a CRT monitor 47521.3.2 Horizontal synchronization 47621.3.3 Vertical synchronization 47821.3.4 Pixel clock rate 47921.3.5 VGA synchronization circuit 48021.4 Bar test-pattern generator 48321.5 Color-to-grayscale conversion circuit 48521.6 Demo video system 48621.7 Advanced video standards 48821.8 Bibliographic notes 48921.9 Suggested experiments 48921.9.1 Horizontal bar test-pattern generator 48921.9.2 Color channel selection circuit 48921.9.3 Enhanced color-to-grayscale conversion circuit 48921.9.4 Square test-pattern generator: part I 48921.9.5 Square test-pattern generator: part II 48921.9.6 Square test-pattern generator: part III 49021.9.7 Square test-pattern generator: part IV 49022 FPro Video Subsystem 49122.1 Organization of the video subsystem 49122.1.1 Overview 49122.1.2 Video controller 49322.1.3 HDL of the video controller 49422.2 FPro video IP core 49522.2.1 Basic functionality 49522.2.2 Blending operation 49622.2.3 Core architecture 49822.2.4 Alternative core partition 50022.3 Example video cores 50022.3.1 Bar test-pattern generator core 50022.3.2 Color-to-grayscale conversion core 50322.3.3 “Dummy” core 50422.4 FPro video synchronization core 50422.4.1 Line buffer 50522.4.2 Enhanced video synchronization circuit 50822.4.3 HDL code 51122.5 Daisy video subsystem 51222.5.1 Subsystem overview 51222.5.2 Interface to the video synchronization core 51322.5.3 HDL code 51322.5.4 Timing and performance considerations 51722.6 Vanilla daisy FPro system 51722.6.1 Clock management core 51822.6.2 Updated chu_io_map.svh 51922.6.3 HDL code 51922.7 Video driver and test program 52122.7.1 Updated chu_io_map.h and chu_io_rw.h files 52122.7.2 GPV core driver 52222.7.3 Test program 52322.8 Bibliographic notes 52422.9 Suggested experiments 52522.9.1 Color channel selection core 52522.9.2 Enhanced color-to-grayscale conversion core 52522.9.3 Square test-pattern generator core 52522.9.4 Alpha blending circuit 52522.9.5 “Highlight” core 52522.9.6 SVGA synchronization core 52622.9.7 Configurable video synchronization core 52622.9.8 Pipelined video subsystem 52623 Sprite Core 52723.1 Introduction 52723.2 Basic design 52823.2.1 Sprite RAM 52823.2.2 In-region comparison circuit 52923.3 Mouse pointer core 53023.3.1 Pointer sprite RAM 53023.3.2 Pixel generation circuit 53123.3.3 Top-level design 53223.4 “Ghost” character core 53423.4.1 Multiple images and animation 53423.4.2 Overview of the palette scheme 53523.4.3 Ghost sprite RAM and the palette circuit 53523.4.4 Animation timing circuit 53723.4.5 Pixel generation circuit 53723.4.6 Top-level design 54023.5 Sprite core driver and test program 54123.5.1 Sprite core driver 54123.5.2 Test program 54323.6 Bibliographic notes 54423.7 Suggested experiments 54423.7.1 Mouse pointer control with PS2 core 54423.7.2 Emulated ghost core 54423.7.3 Palette circuit for the mouse pointer sprite 54423.7.4 Sprite scaling circuit 54423.7.5 Portrait mode display 54523.7.6 Multiple-object generation 54523.7.7 Animation speed control 54523.7.8 Imitated blinking LED: part I 54523.7.9 Imitated blinking LED: part II 54523.7.10 Imitated blinking LED: part III 54624 On-Screen-Display Core 54724.1 Introduction to tile graphics 54724.2 Basic OSD design 54924.2.1 Text-mode display 54924.2.2 Font ROM 55024.2.3 Tile RAM 55024.2.4 Basic organization 55124.3 OSD core 55224.3.1 Font ROM 55224.3.2 Pixel generation circuit 55324.3.3 Top-level design 55524.4 OSD core driver and test program 55724.4.1 OSD core driver 55724.4.2 Testing program 55824.5 Bibliographic notes 55924.6 Suggested experiments 55924.6.1 Rotating banner 55924.6.2 Text console 55924.6.3 Underline for the cursor 55924.6.4 Portrait-mode display 56024.6.5 Font scaling circuit: part I 56024.6.6 Font scaling circuit: part II 56024.6.7 Extended font 56024.6.8 Tile-based ghost core 56025 VGA Frame Buffer Core 56125.1 Overview 56125.2 Frame buffer core 56225.2.1 FPGA memory consideration 56225.2.2 Video memory module 56225.2.3 Address translation 56325.2.4 Pixel generation circuit 56425.2.5 Register map 56625.2.6 Top-level HDL code 56625.3 Driver and test program 56725.3.1 Frame buffer core driver 56725.3.2 Geometrical modeling 56825.3.3 Test program 57025.4 Project ideas 57025.5 Bibliographic notes 57225.6 Suggested experiments 57225.6.1 Virtual prototyping board panel 57225.6.2 Virtual analog wall clock 57225.6.3 Geometrical model functions 57225.6.4 Simulated “Etch a Sketch” toy 57225.6.5 Frame buffer core with 3-bit color depth 57325.6.6 Frame buffer core with 1-bit color depth 57325.6.7 QVGA frame buffer core 57325.6.8 Line drawing hardware accelerator 57325.6.9 Bidirectional frame buffer access: part I 57325.6.10 Bidirectional frame buffer access: part II 573PART V EPILOGUE26 What’s Next 577References 581Appendix A: Tutorials 585A.1 Overview of Xilinx Vivado IDE 585A.2 Short tutorial on Vivado hardware development 589A.2.1 Create a design project 590A.2.2 Add or create Xilinx IP core instances 591A.2.3 Add or create HDL design files 591A.2.4 Add a constraint file 592A.2.5 Perform synthesis, implementation, and bitstream generation 593A.2.6 Program an FPGA device 593A.3 Short tutorial on Vivado simulation 594A.3.1 Add or create HDL testbench 596A.3.2 Perform initial simulation 596A.3.3 Customize waveform display 597A.4 Tutorial on IP instantiation 597A.4.1 Dual-clock FIFO core via HDL templates 598A.4.2 IP Catalog utility 599A.4.3 Generate a MicroBlaze MCS component 600A.4.4 XADC IP core 601A.4.5 Clock management IP core 602A.5 Short tutorial on FPro system development 604A.5.1 Derive FPro system hardware 605A.5.2 Export hardware configuration 605A.5.3 Derive software 605A.5.4 Embed elf file into FPGA’s memory module and regenerate bitstream 608A.5.5 Set up the terminal emulator program 610A.5.6 Program an FPGA device 610A.6 Bibliographic notes 611Topic Index 613

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