Emerging Nanoelectronic Devices

An Chen is with GLOBALFOUNDRIES, working on emerging logic and memory technologies.  He is the Memory Technology Lead responsible for exploratory memory research with industrial consortia including IMEC and Sematech.  His memory research focuses primarily on RRAM and STTRAM.  Prior to GLOBALFOUNDRIES, he worked at Spansion LLC on emerging memory research and at Advanced Micro Devices (AMD) on nanoelectronics.  He is currently chairing the Emerging Research Device (ERD) working group in the International Technology Roadmap of Semiconductors (ITRS).  He is also a Senior Member of the IEEE. James Hutchby, Senior Scientist, Emeritus, was formerly Director of Device Sciences of Semiconductor Research Corporation (SRC). Prior to joining SRC he was founding Director of the Research Triangle Institute’s Center for Semiconductor Research, which consisted of five research groups performing research on: low-temperature growth of diamond; high efficiency multi-bandgap solar cells; complementary HBT devices and integrated circuits and high efficiency thermoelectrics and theremovoltaics. Dr Hutchby has authored or co-authored over 160 contributed and invited papers.  He is also a Life Fellow of the IEEE and a recipient of the IEEE Third Millennium Medal. Victor Zhirnov is Director of Special Projects at the SRC. His research interests include nanoelectronics devices and systems, properties of materials at the nanoscale and bio-inspired electronic systems. He also holds an adjunct faculty position at North Carolina State University and has served as an advisor to a number of government, industrial, and academic institutions. Victor Zhirnov has authored and co-authored over 100 technical papers and contributions to books. George Bourianoff is a Senior Principle Engineer in the Components Research group at Intel. He is responsible for developing and managing research programs in emerging research technologies and architectures.  He also serves on the scientific advisory boards of the Nanoelectronic Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network. (STARnet).  Prior to joining Intel in 1994 Dr Bourianoff was a group leader in the Superconducting Supercollidier Project in Texas responsible for accelerator simulation.  Prior to that, he was a Senior Scientist with SAIC responsible for Magneto Hydrodynamic code development.

• Preface xixList of Contributors xxiAcronyms xxiiiPART ONE INTRODUCTION 11 The Nanoelectronics Roadmap 3James Hutchby1.1 Introduction 31.2 Technology Scaling: Impact and Issues 41.3 Technology Scaling: Scaling Limits of Charge-based Devices 41.4 The International Technology Roadmap for Semiconductors 61.5 ITRS Emerging Research Devices International Technology Working Group 71.6 Guiding Performance Criteria 81.7 Selection of Nanodevices as Technology Entries 131.8 Perspectives 13References 142 What Constitutes a Nanoswitch? A Perspective 15Supriyo Datta, Vinh Quang Diep, and Behtash Behin-Aein2.1 The Search for a Better Switch 152.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain 172.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain? 202.4 Giant Spin Hall Effect: A Route to Gain 232.5 Other Possibilities for Switches with Gain 272.6 What do Alternative Switches Have to Offer? 292.7 Perspective 322.8 Summary 32Acknowledgments 32References 33PART TWO NANOELECTRONIC MEMORIES 353 Memory Technologies: Status and Perspectives 37Victor V. Zhirnov and Matthew J. Marinella3.1 Introduction: Baseline Memory Technologies 373.2 Essential Physics of Charge-based Memory 383.3 Dynamic Random Access Memory 393.4 Flash Memory 433.5 Static Random Access Memory 493.6 Summary and Perspective 52Appendix: Memory Array Interconnects 52Acknowledgments 54References 544 Spin Transfer Torque Random Access Memory 56Jian-Ping Wang, Mahdi Jamali, Angeline Klemm, and Hao Meng4.1 Chapter Overview 564.2 Spin Transfer Torque 574.3 STT-RAM Operation 604.4 STT-RAM with Perpendicular Anisotropy 634.5 Stack and Material Engineering for Jc Reduction 664.6 Ultra-Fast Switching of MTJs 714.7 Spin–Orbit Torques for Memory Application 724.8 Current Demonstrations for STT-RAM 734.9 Summary and Perspectives 73References 745 Phase Change Memory 78Rakesh Jeyasingh, Ethan C. Ahn, S. Burc Eryilmaz, Scott Fong, and H.-S. Philip Wong5.1 Introduction 785.2 Device Operation 795.3 Material Properties 805.4 Device and Material Scaling to the Nanometer Size 885.5 Multi-Bit Operation and 3D Integration 935.6 Applications 975.7 Future Outlook 1005.8 Summary 103Acknowledgments 103References 1036 Ferroelectric FET Memory 110Ken Takeuchi and An Chen6.1 Introduction 1106.2 Ferroelectric FET for Flash Memory Application 1116.3 Ferroelectric FET for SRAM Application 1156.4 System Consideration: SSD System with Fe-NAND Flash Memory 1186.5 Perspectives and Summary 119References 1207 Nano-Electro-Mechanical (NEM) Memory Devices 123Adrian M. Ionescu7.1 Introduction and Rationale for a Memory Based on NEM Switch 1237.2 NEM Relay and Capacitor Memories 1267.3 NEM-FET Memory 1307.4 Carbon-based NEM Memories 1327.5 Opportunities and Challenges for NEM Memories 133References 1358 Redox-based Resistive Memory 137Stephan Menzel, Eike Linn, and Rainer Waser8.1 Introduction 1378.2 Physical Fundamentals of Redox Memories 1398.3 Electrochemical Metallization Memory Cells 1448.4 Valence Change Memory Cells 1498.5 Performance 1548.6 Summary 158References 1589 Electronic Effect Resistive Switching Memories 162An Chen9.1 Introduction 1629.2 Charge Injection and Trapping 1649.3 Mott Transition 1679.4 Ferroelectric Resistive Switching 1709.5 Perspectives 1739.6 Summary 176References 17610 Macromolecular Memory 181Benjamin F. Bory and Stefan C.J. Meskers10.1 Chapter Overview 18110.2 Macromolecules 18110.3 Elementary Physical Chemistry of Macromolecular Memory 18410.4 Classes of Macromolecular Memory Materials and Their Performance 18710.5 Perspectives 19010.6 Summary 190Acknowledgments 190References 19111 Molecular Transistors 194Mark A. Reed, Hyunwook Song, and Takhee Lee11.1 Introduction 19411.2 Experimental Approaches 19411.3 Molecular Transistors 21311.4 Molecular Design 21811.5 Perspectives 222Acknowledgments 223References 22312 Memory Select Devices 227An Chen12.1 Introduction 22712.2 Crossbar Array and Memory Select Devices 22712.3 Memory Select Device Options 23012.4 Challenges of Memory Select Devices 24112.5 Summary 242References 24213 Emerging Memory Devices: Assessment and Benchmarking 246Matthew J. Marinella and Victor V. Zhirnov13.1 Introduction 24613.2 Common Emerging Memory Terminology and Metrics 24813.3 Redox RAM 24913.4 Emerging Ferroelectric Memories 25413.5 Mott Memory 25813.6 Macromolecular Memory 25913.7 Carbon-based Resistive Switching Memory 26013.8 Molecular Memory 26213.9 Assessment and Benchmarking 26313.10 Summary and Conclusions 271Acknowledgments 271References 271PART THREE NANOELECTRONIC LOGIC AND INFORMATION PROCESSING 27714 Re-Invention of FET 279Toshiro Hiramoto14.1 Introduction 27914.2 Historical and Future Trend of MOSFETs 27914.3 Near-term Solutions 28214.4 Long-term Solutions 28514.5 Summary 295References 29615 Graphene Electronics 298Frank Schwierz15.1 Introduction 29815.2 Properties of Graphene 30015.3 Graphene MOSFETs for Mainstream Logic and RF Applications 30315.4 Graphene MOSFETs for Nonmainstream Applications 30815.5 Graphene NonMOSFET Transistors 30915.6 Perspectives 310Acknowledgment 311References 31116 Carbon Nanotube Electronics 315Aaron D. Franklin16.1 Carbon Nanotubes – The Ideal Transistor Channel 31516.2 Operation of the CNTFET 31916.3 Important Aspects of CNTFETs 32016.4 Scaling CNTFETs to the Sub-10 Nanometer Regime 32416.5 Material Considerations 32716.6 Perspective 32916.7 Conclusion 331References 33117 Spintronics 336Alexander Khitun17.1 Introduction 33617.2 Spin Transistors 33717.3 Magnetic Logic Circuits 34817.4 Summary 364References 36518 NEMS Switch Technology 370Louis Hutin and Tsu-Jae King Liu18.1 Electromechanical Switches for Digital Logic 37018.2 Actuation Mechanisms 37318.3 Electrostatic Switch Designs 37918.4 Reliability and Scalability 383References 38619 Atomic Switch 390Tsuyoshi Hasegawa and Masakazu Aono19.1 Chapter Overview 39019.2 Historical Background of the Atomic Switch 39019.3 Fundamentals of Atomic Switches 39119.4 Various Atomic Switches 39519.5 Perspectives 401References 40220 ITRS Assessment and Benchmarking of Emerging Logic Devices 405Shamik Das20.1 Introduction 40520.2 Overview of the ITRS Roadmap for Emerging Research Logic Devices 40620.3 Recent Results for Selected Emerging Devices 40720.4 Perspective 41220.5 Summary 413Acknowledgments 413References 413PART FOUR CONCEPTS FOR EMERGING ARCHITECTURES 41721 Nanomagnet Logic: A Magnetic Implementation of Quantum-dot Cellular Automata 419Michael T. Niemier, György Csaba, and Wolfgang Porod21.1 Introduction 41921.2 Technology Background 42021.3 NML Circuit Design Based on Conventional, Boolean Logic Gates 42321.4 Alternative Circuit Design Techniques and Architectures 43221.5 Retrospective, Future Challenges, and Future Research Directions 437References 43922 Explorations in Morphic Architectures 443Tetsuya Asai and Ferdinand Peper22.1 Introduction 44322.2 Neuromorphic Architectures 44322.3 Cellular Automata Architectures 44722.4 Taxonomy of Computational Ability of Architectures 45022.5 Summary 452References 45223 Design Considerations for a Computational Architecture of Human Cognition 456Narayan Srinivasa23.1 Introduction 45623.2 Features of Biological Computation 45723.3 Evolution of Behavior as a Basis for Cognitive Architecture Design 46023.4 Considerations for a Cognitive Architecture 46023.5 Emergent Cognition 46323.6 Perspectives 463References 46424 Alternative Architectures for NonBoolean Information Processing Systems 467Yan Fang, Steven P. Levitan, Donald M. Chiarulli, and Denver H. Dash24.1 Introduction 46724.2 Hierarchical Associative Memory Models 47524.3 N-Tree Model 48424.4 Summary and Conclusion 494Acknowledgments 496References 49625 Storage Class Memory 498Geoffrey W. Burr and Paul Franzon25.1 Introduction 49825.2 Traditional Storage: HDD and Flash Solid-state Drives 49925.3 What is Storage Class Memory? 49925.4 Target Specifications for SCM 50125.5 Device Candidates for SCM 50225.6 Architectural Issues in SCM 50425.7 Conclusions 508References 509PART FIVE SUMMARY, CONCLUSIONS, AND OUTLOOK FOR NANOELECTRONIC DEVICES 51126 Outlook for Nanoelectronic Devices 513An Chen, James Hutchby, Victor V. Zhirnov, and George Bourianoff26.1 Introduction 51326.2 Quantitative Logic Benchmarking for Beyond CMOS Technologies 51426.3 Survey-based Critical Assessment of Emerging Devices 51826.4 Retrospective Assessment of ERD Tracked Technologies 526References 528Index 529