Sanjay Churiwala - Böcker

Principles of VLSI RTL Design

A Practical Guide

Constraining Designs for Synthesis and Timing Analysis

A Practical Guide to Synopsys Design Constraints (SDC)

Constraining Designs for Synthesis and Timing Analysis

A Practical Guide to Synopsys Design Constraints (SDC)

Principles of VLSI RTL Design

A Practical Guide

Introduction to Machine Learning

Designing with Xilinx® FPGAs

Using Vivado