Vertical 3D Memory Technologies

Dr Betty Prince has over 30 years’ experience in the semiconductor industry having worked with Texas Instruments, N.V. Philips, Motorola, R.C.A., and Fairchild and is currently CEO of Memory Strategies International. She has authored four books and served from 1991-1994 on the Technical Advisory Board of IEEE Spectrum magazine. She is a Senior Life Member of the IEEE and served as an IEEE SSCS Distinguished Lecturer and on the Program Committee of the IEEE Custom Integrated Circuit conference. She was founder of the JEDEC JC-16 Interface Standards Committee and was active for many years on the JC-42 Memory Committee where she was co-chair of the SRAM standards group. She has been U.S. representative to the IEC SC47A WG3 Memory Standards Committee. Dr Prince has served on the Technical Advisory Board of several memory companies and has been on the Board of Directors of Mosaid Technologies. She holds patents in the memory, processor and interface areas and has degrees in Physics, Math, and Finance with doctoral dissertation in fractal modeling.

• Acknowledgments xv 1 Basic Memory Device Trends Toward the Vertical 11.1 Overview of 3D Vertical Memory Book 11.2 Moore’s Law and Scaling 21.3 Early RAM 3D Memory 31.3.1 SRAM as the First 3D Memory 31.3.2 An Early 3D Memory—The FinFET SRAM 61.3.3 Early Progress in 3D DRAM Trench and Stack Capacitors 61.3.4 3D as the Next Step for Embedded RAM 111.4 Early Nonvolatile Memories Evolve to 3D 131.4.1 NOR Flash Memory—Both Standalone and Embedded 131.4.2 The Charge-Trapping EEPROM 141.4.3 Thin-Film Transistor Takes Nonvolatile Memory into 3D 151.4.4 3D Microcontroller Stacks with Embedded SRAM and EEPROM 171.4.5 NAND Flash Memory as an Ideal 3D Memory 171.5 3D Cross-Point Arrays with Resistance RAM 201.6 STT-MTJ Resistance Switches in 3D 211.7 The Role of Emerging Memories in 3D Vertical Memories 22References 232 3D Memory Using Double-Gate, Folded, TFT, and Stacked Crystal Silicon 252.1 Introduction 252.2 FinFET—Early Vertical Memories 262.2.1 Early FD-SOI FinFET Charge-Trapping Flash Memory 262.2.2 FinFET Charge-Trapping Memory on Bulk Silicon 282.2.3 Doubling Memory Density Using a Paired FinFET Bit-Line Structure 322.2.4 Other Folded Gate Memory Structures and Characteristics 342.3 Double-Gate and Tri-Gate Flash 372.3.1 Vertical Channel Double Floating Gate Flash Memory 372.3.2 Early Double- and Tri-Gate FinFET Charge-Trapping Flash Memories 382.3.3 Double-Gate Dopant-Segregated Schottky Barrier CT FinFET Flash 392.3.4 Independent Double-Gate FinFET CT Flash Memory 422.4 Thin-Film Transistor (TFT) Nonvolatile Memory with Polysilicon Channels 432.4.1 Independent Double-Gate Memory with TFT and Polysilicon Channels 432.4.2 TFT Polysilicon Channel NV Memory Using Silicon Protrusions to Enhance Performance 462.4.3 An Improved Polysilicon Channel TFT for Vertical Transistor NAND Flash 462.4.4 Polysilicon TFT CT Memory with Vacuum Tunneling and Al2O3 Blocking Oxide 472.4.5 Graphene Channel NV Memory with Al2O3–HfOx–Al2O3 Storage Layer 482.5 Double-Gate Vertical Channel Flash Memory with Engineered Tunnel Layer 492.5.1 Double-Gate Vertical Single-Crystal Silicon Channel with Engineered Tunnel Layer 492.5.2 Polysilicon Substrate TFT CT NAND with Engineered Tunnel Layer 512.5.3 Polysilicon Channel Double-Layer Stacked TFT NAND Bandgap-Engineered Flash 522.5.4 Eight-Layer 3D Vertical DG TFT NAND Flash with Junctionless Buried Channel 542.5.5 Variability in Polysilicon TFT for 3D Vertical Gate NAND Flash 552.6 Stacked Gated Twin-Bit (SGTB) CT Flash 552.7 Crystalline Silicon and Epitaxial Stacked Layers 562.7.1 Stacked Crystalline Silicon Layer TFT for Six-Transistor SRAM Cell Technology 572.7.2 Stacked Silicon Layer S3 Process for Production SRAM 612.7.3 NAND Flash Memory Development Using Double-Stacked S3 Technology 642.7.4 4Gb NAND Flash Memory in 45 nm 3D Double-Stacked S3 Technology 66References 693 Gate-All-Around (GAA) Nanowire for Vertical Memory 723.1 Overview of GAA Nanowire Memories 723.2 Single-Crystal Silicon GAA Nanowire CT Memories 723.2.1 Overview of Single-Crystal Silicon GAA CT Memories 723.2.2 An Early GAA Nanowire Single-Crystal Silicon CT Memory 733.2.3 Vertically Stacked Single-Crystal Silicon Twin Nanowire GAA CT Memories 743.2.4 GAA CT NAND Flash String Using One Single-Crystal SiNW 753.2.5 Single-Crystal SiNW CT Memory with High-κ Dielectric and Metal Gate 773.2.6 Improvement in Transient Vth Shift After Erase in 3D GAA NW SONOS 783.2.7 Semianalytical Model of GAA CT Memories 793.2.8 Nonvolatile GAA Single-Crystal Silicon Nanowire Memory on Bulk Substrate 793.3 Polysilicon GAA Nanowire CT Memories 823.3.1 Polysilicon CT Memories with NW Diameter Comparable to Polysilicon Grain Size 823.3.2 Various GAA Polysilicon NW Memory Configurations 833.3.3 Trapping Layer Enhanced Polysilicon NW SONOS 853.4 Junctionless GAA CT Nanowire Memories 883.4.1 3D Junctionless Vertical GAA Silicon NW SONOS Memories 883.4.2 Junctionless GAA SONOS Silicon Nanowire on Bulk Substrate for 3D NAND Stack 913.4.3 Modeling Erase in Cylindrical Junctionless CT Arrays 923.4.4 HfO2–Si3N4 Trap Layer in Junctionless Polycrystal GAA Memory Storage 953.5 3D Stacked Horizontal Nanowire Single-Crystal Silicon Memory 953.5.1 Process for 3D Stacked Horizontal NW Single-Crystal Silicon Memory 963.5.2 A Stacked Horizontal NW Single-Crystal Silicon NAND Flash Memory Development 983.6 Vertical Single-Crystal GAA CT Nanowire Flash Technology 1033.6.1 Overview of Vertical Flash Using GAA SONOS Nanowire Technology 1033.6.2 Vertical Single-Crystal Silicon 3D Flash Using GAA SONOS Nanowire 1033.6.3 Fabrication of Two Independent GAA FETs on a Vertical SiNW 1043.6.4 Vertical 3D Silicon Nanowire CT NAND Array 1063.7 Vertical Channel Polysilicon GAA CT Memory 1073.7.1 Multiple Vertical GAA Flash Cells Stacked Using Polysilicon NW Channel 1073.7.2 Vth Shift Characteristics of Vertical GAA SONOS and/or TANOS Nonvolatile Memory 1093.7.3 GAA Vertical Pipe CT Gate Replacement Technology 1113.7.4 Bilayer Poly Channel Vertical Flash for 3D SONOS NAND 1123.7.5 3D Vertical Pipe CT Low-Resistance (CoSi) Word-Line NAND Flash 1123.7.6 Vertical Channel CT 3D NAND Flash Cell 1143.7.7 Read Sensing for Thin-Body Vertical NAND 1143.8 Graphene Channel Nonvolatile Memory with Al2O3–HfOx–Al2O3 Storage Layer 1153.9 Cost Analysis for 3D GAA NAND Flash Considering Channel Slope 116References 1174 Vertical NAND Flash 1194.1 Overview of 3D Vertical NAND Trends 1194.1.1 3D Nonvolatile Memory Overview 1194.1.2 Architectures of Various 3D NAND Flash Arrays 1204.1.3 Scaling Trends for 2D and 3D NAND Cells 1224.2 Vertical Channel (Pipe) CT NAND Flash Technology 1244.2.1 BiCS CT Pipe NAND Flash Technology 1244.2.2 Pipe-Shaped BiCS (P-BiCS) NAND Flash Technology 1284.2.3 Vertical CT Vertical Recess Array Transistor (VRAT) Technology 1384.2.4 Z-VRAT CT Memory Technology 1394.2.5 Vertical NAND Chains—VSAT with “PIPE” Process 1414.2.6 Vertical CT PIPE NAND Flash with Damascene Metal Gate TCAT/VNAND 1424.2.7 3D NAND Flash SB-CAT Stack 1454.3 3D FG NAND Flash Cell Arrays 1464.3.1 3D FG NAND with Extended Sidewall Control Gate 1464.3.2 3D FG NAND with Separated-Sidewall Control Gate 1494.3.3 3D FG NAND Flash Cell with Dual CGs and Surrounding FG (DC-SF) 1524.3.4 3D Vertical FG NAND with Sidewall Control Pillar 1554.3.5 Trap Characterization in 3D Vertical Channel NAND Flash 1574.3.6 Program Disturb Characteristics of 3D Vertical NAND Flash 1584.4 3D Stacked NAND Flash with Lateral BL Layers and Vertical Gate 1594.4.1 Introduction to Horizontal BL and Vertical Gate NAND Flash 1594.4.2 A 3D Vertical Gate NAND Flash Process and Device Considerations 1604.4.3 Vertical Gate NAND Flash Integration with Eight Active Layers 1634.4.4 3D Stacked CT TFT Bandgap-Engineered SONOS NAND Flash Memory 1654.4.5 Horizontal Channel Vertical Gate 3D NAND Flash with PN Diode Decoding 1684.4.6 3D Vertical Gate BE-SONOS NAND Program Inhibit with Multiple Island Gate Decoding 1694.4.7 3D Vertical Gate NAND Flash BL Decoding and Page Operation 1714.4.8 An Eight-Layer Vertical Gate 3D NAND Architecture with Split-Page BL 1734.4.9 Various Innovations for 3D Stackable Vertical Gate 1764.4.10 Variability Considerations in 2D Vertical Gate 3D NAND Flash 1804.4.11 An Etching Technology for Vertical Multilayers for 3D Vertical Gate NAND Flash 1824.4.12 Interference, Disturb, and Programming Algorithms for MLC Vertical Gate NAND 1834.4.13 3D Vertical Gate NAND Flash Program and Read and Fail-Bit Detection 1844.4.14 3D p-Channel Stackable NAND Flash with Band-to-Band Tunnel Programming 1854.4.15 A Bit-Alterable 3D NAND Flash with n-Channel and p-Channel NAND 187References 1895 3D Cross-Point Array Memory 1925.1 Overview of Cross-Point Array Memory 1925.2 A Brief Background of Cross-Point Array Memories 1935.2.1 Construction of a Basic Cross-Point Array 1935.2.2 Stacking Multibit Cross-Point Arrays 1945.2.3 Methods of Stacking Cross-Point Arrays 1965.2.4 Stacking Cross-Point Layers for High Density 1975.2.5 An Example of Unipolar ReRAM 1985.2.6 An Example of a Bipolar ReRAM 1995.2.7 Basic Cross-Point Array Operation with a Diode Selector 2005.2.8 Early Test Chip Using a ReRAM Cross-Point Array with Diode Selector 2015.3 Low-Resistance Interconnects for Cross-Point Arrays 2035.3.1 Model of Low Resistance Interconnects for Cross-Point Arrays 2035.3.2 A Cross-Point Array Grid with Low-Resistivity Nanowires 2065.3.3 A Cross-Point Array Using Two Nickel Core Nanowires 2065.3.4 Resistive Memory Using Single-Wall Carbon Nanotubes 2075.4 Cross-Point Array Memories Without Cell Selectors 2075.4.1 Early Model of Bipolar Resistive Switch in Selectorless Cross-Point Array 2085.4.2 Sneak Path Leakage in a Selectorless Cross-Point Array 2105.4.3 Effect of Parasitic Resistance on Maximum Size of a Selectorless Cross-Point Array 2125.4.4 Effect of Nonlinearity on I–V Characteristics of Selectorless Memory Element 2155.4.5 Self-Rectifying ReRAM Requirements in Cross-Point Arrays 2165.4.6 A Cross-Point Array Model for Line Resistance and Nonlinear Devices 2175.5 Examples of Selectorless Cross-Point Arrays 2175.5.1 Example of Nonlinearity in a Selectorless Cross-Point Array 2175.5.2 Example of High-Resistive Memory Element in Selectorless Cross-Point Array 2185.5.3 Design Techniques for Nonlinear Selectorless Cross-Point Arrays Using ReRAMs 2215.5.4 Film Thickness and Scaling Effects in Cross-Point Selectorless ReRAM 2225.5.5 Vertical HfOx ReRAM 3D Cross-Point Array Without Cell Selector 2235.5.6 Dopant Selection Rules for Tuning HfOx ReRAM Characteristics 2245.5.7 High-Resistance CB-ReRAM Memory Element to Avoid Sneak Current 2255.5.8 Electromechanical Diode Cell for a Cross-Point Nonvolatile Memory Array 2265.6 Unipolar Resistance RAMs with Diode Selectors in Cross-Point Arrays 2275.6.1 Overview of Unipolar ReRAMS with Diode Selectors in Cross-Point Arrays 2275.6.2 A Unipolar ReRAM with Silicon Diode for Cross-Point Array 2285.6.3 CuOx–InZnOx Heterojunction Thin-Film Diode with NiO ReRAM 2305.6.4 Unipolar NiO ReRAM Ireset and SET–RESET Instability 2325.6.5 HfOx–AlOy Unipolar ReRAM with Silicon Diode Selector in Cross-Point Array 2325.6.6 TiN–TaOx–Pt MIM Selector for Pt–TaOx–Pt Unipolar ReRAM Cross-Point Array 2345.6.7 Self-Rectifying Unipolar Ni–HfOx Schottky Barrier ReRAM 2345.6.8 Schottky Barriers for Self-Rectifying Unidirectional Cross-Point Array 2365.6.9 Thermally Induced Set Operation for Unipolar ReRAM with Diode Selector 2375.7 Unipolar PCM with Two-Terminal Diodes for Cross-Point Array 2385.7.1 Background of Phase-Change Memory in a Cross-Point Array 2385.7.2 PCMs in Cross-Point Arrays with Polysilicon Diodes 2395.7.3 Cross-Point Array with PCM and Carbon Nanotube Electrode 2405.7.4 Cross-Point Array with MIEC Access Devices and PCM Elements 2415.7.5 Threshold Switching Access Devices for ReRAM Cross-Point Arrays 2435.7.6 p–n Diode Selection Devices for PCM 2445.7.7 Epitaxial Diode Selector for PCM in Cross-Point Arrays 2455.7.8 Dual-Trench Epitaxial Diode Array for High-Density PCM 2455.8 Bipolar Resistance RAMS With Selector Devices in Cross-Point Arrays 2465.8.1 VO2 Select Device for Bipolar ReRAM in Cross-Point Array 2465.8.2 Threshold Select Devices for Bipolar Memory Elements in Cross-Point Arrays 2465.8.3 Vertical Bipolar Switching Polysilicon n–p–n Diode for Cross-Point Array 2495.8.4 Two-Terminal Diode Steering Element for 3D Cross-Point ReRAM Array 2505.8.5 Varistor-Type Bidirectional Switch for 3D Bipolar ReRAM Array 2505.8.6 Bidirectional Threshold Vacuum Switch for 3D 4F2 Cross-Point Array 2515.8.7 Bidirectional Schottky Diode Selector 2525.8.8 Bipolar ReRAM with Schottky Self-Rectifying Behavior in the LRS 2545.8.9 Self-Rectifying Bipolar ReRAM Using Schottky Barrier at Ta–TaOx Interface 2555.8.10 Diode Effect of Pt–In2Ga2ZnO7 Layer in TiO2-type ReRAM 2555.8.11 Confined NbO2 as a Selector in Bipolar ReRAMs 2565.9 Complementary Switching Devices and Arrays 2565.9.1 Complementary Resistive Switching for Dense Crossbar Arrays 2565.9.2 CRS Memory Using Amorphous Carbon and CNTs 2575.9.3 Complementary Switching in Metal–Oxide ReRAM for Crossbar Arrays 2595.9.4 CRSs Using a Heterodevice 2605.9.5 Self-Selective W–VO2–Pt ReRAM to Reduce Sneak Current in ReRAM Arrays 2615.9.6 Hybrid Nb2O5–NbO2 ReRAMwith Combined Memory and Selector 2635.9.7 Analysis of Complementary ReRAM Switching 2645.9.8 Complementary Stacked Bipolar ReRAM Cross-Point Arrays 2665.9.9 Complementary Switching Oxide-Based Bipolar ReRAM 2665.10 Toward Manufacturable ReRAM Cells and Cross-point Arrays 2675.10.1 28 nm ReRAM and Diode Cross-Point Array in CMOS-Compatible Process 2675.10.2 Double-Layer 3D Vertical ReRAM for High-Density Arrays 2685.10.3 Study of Cell Performance for Different Stacked ReRAM Geometries 2695.11 STT Magnetic Tunnel Junction Resistance Switches in Cross-Point Array Architecture 2695.11.1 High-Density Cross-Point STT Magnetic Tunnel Junction Architecture 269References 2716 3D Stacking of RAM–Processor Chips Using TSV 2756.1 Overview of 3D Stacking of RAM–Processor Chips with TSV 2756.2 Architecture and Design of TSV RAM–Processor Chips 2806.2.1 Overview of Architecture and Design of Vertical TSV Connected Chips 2806.2.2 Repartitioning For Performance by Increasing the Number of Memory Banks 2806.2.3 Using a Global Clock Distribution Technique to Improve Performance 2826.2.4 Stacking eDRAM Cache and Processor for Improved Performance 2826.2.5 Using Decoupling Scheduling of the Memory Controller to Improve Performance 2836.2.6 Repartitioning Multicore Processors and Stacked RAM for Improved Performance 2836.2.7 Increasing Performance and Lowering Power in Low-Power Mobile Systems 2876.2.8 Increasing Performance of Memory Hierarchies with 3D TSV Integration 2876.2.9 Adding Storage-Class Memory to the Memory Hierarchy 2896.2.10 Improving Performance Using 3D Stacked RAM Modeling 2906.3 Process and Fabrication of Vertical TSV for Memory and Logic 2926.3.1 Passive TSV Interposers for Stacked Memory–Logic Integration 2926.3.2 Process Fabrication Methods and Foundries for Early 2.5D and 3D Integration 2956.3.3 Integration with TSV Using a High-κ–Metal Gate CMOS Process 2966.3.4 Processor with Deep Trench DRAM TSV Stacks and High-κ–Metal Gate 2976.4 Process and Fabrication Issues of TSV 3D Stacking Technology 2996.4.1 Using Copper TSV for 3D Stacking 2996.4.2 Air Gaps for High-Performance TSV Interconnects for 3D ICs 3006.5 Fabrication of TSVs 3016.5.1 Using TSVs at Various Stages in the Process 3016.5.2 Stacked Chips using Via-Middle Technology 3036.6 Energy Efficiency Considerations of 3D Stacked Memory–Logic Chip Systems 3066.6.1 Overview of Energy Efficiency in 3D Stacked Memory–Logic Chip Systems 3066.6.2 Energy Efficiency for a 3D TSV Integrated DRAM–Controller System 3066.6.3 Adding an SRAM Row Cache to Stacked 3D DRAM to Minimize Energy 3086.6.4 Power Delivery Networks in 3D ICs 3116.6.5 Using Near-Threshold Computing for Power Reduction in a 3D TSV System 3126.7 Thermal Characterization Analysis and Modeling of RAM–Logic Stacks 3146.7.1 Thermal Management of Hot Spots in 3D Chips 3146.7.2 Thermal Management in 3D Chips Using an Interposer with Embedded TSV 3146.7.3 Thermal Management of TSV DRAM Stacks with Logic 3146.7.4 Thermal Management of a 3D TSV SRAM on Logic Stack 3166.8 Testing of 3D Stacked TSV System Chips 3166.8.1 Using BIST to Reduce Testing for a Logic and DRAM System Stack 3166.8.2 Efficient BISR and Redundancy Allocation in 3D RAM–Logic Stacks 3166.8.3 Direct Testing of Early SDRAM Stacks 3196.9 Reliability Considerations with 3D TSV RAM–Processor Chips 3206.9.1 Overview of Reliability Issues in 3D TSV Stacked RAM–Processor Chips 3206.9.2 Variation Issues in Stacked 3D TSV RAM–Processor Chips 3206.9.3 Switching and Decoupling Noise in a 3D TSV-Based System 3216.9.4 TSV-Induced Mechanical Stress in CMOS 3246.10 Reconfiguring Stacked TSV Memory Architectures for Improved Performance 3266.10.1 Overview of Potential for Reconfigured Stacked Architectures 3266.10.2 3D TSV-based 3D SRAM for High-Performance Platforms 3266.10.3 Waveform Capture with 100 GB/s I/O, 4096 TSVs and an Active Si Interposer 3296.10.4 3D Stacked FPGA and ReRAM Configuration Memory 3306.10.5 Cache Architecture to Configure Stacked DRAM to Specific Applications 3306.10.6 Network Platform for Stacked Memory–Processor Architectures 3316.10.7 Multiplexing Signals to Reduce Number of TSVs in IC Die Stacking 3326.10.8 3D Hybrid Cache with MRAM and SRAM Stacked on Processor Cores 3336.10.9 CMOS FPGA and Routing Switches Made with ReRAM Devices 3336.10.10 Dynamic Configurable SRAM Stacked with Various Logic Chips 3336.11 Stacking Memories Using Noncontact Connections with Inductive Coupling 3336.11.1 Overview of Noncontact Inductive Coupling of Stacked Memory 3336.11.2 Early Concepts of Inductive-Coupling Connections of Stacked Memory Chips 3346.11.3 Evolution of Inductive-Coupling Connections of NAND Flash Stacks 3366.11.4 TCI for Replacing Stacking with TSV Connections 3386.11.5 Processor–SRAM 3D Integration Using Inductive Coupling 3396.11.6 Optical Interface for Future 3D Stacked Chip Connections 339References 340Index 345

"In summary, Betty Prince has produced a piece of work that is timely and will undoubtedly become a classic text for 3D memory technologies." (3dincites.com, 30 September 2014)"As the semiconductor memory industry moves to the third dimension a plethora of competing technologies has arisen each claiming to be the logical, lucrative successor to existing two dimensional versions. The very breadth of these new technologies can be confusing even to experienced industry professionals. Dr Prince's book appears at the right time to remove this confusion by explaining each technology's structure, function and potential advantages in a way that is accessible to both interested spectators and those working in the industry. It provides a welcome solid foundation to anyone interested in understanding the various technologies vying for success in this migration."—Andrew Walker, Schiltron Corporation, USA"This is a great review on the current state-of-the-art in the highly topical subject of vertical 3D memories. It comprises the challenges and current solutions of 3D memory integration with respective to different memory technologies. It is a highly valuable resource for researchers and engineers in the field of memory technology."—Dr. Stephan Menzel, Forschungszentrum Jülich (PGI-7), Germany"... one to consider if you want to bring yourself up to speed on recent research behind today's and tomorrow’s 3D memory technologies. The book provides capsule summaries of over 360 papers and articles from scholarly journals organized into sections of related technologies to provide an invaluable reference on a particular 3D technology. It's a useful tool for locating research covering any of the numerous 3D technologies that are now finding their way into early production."—Jim Handy, TheMemoryGuy.com, OBJECTIVE ANALYSIS Semiconductor Market Research, USA