Multi-voltage CMOS Circuit Design

DR VOLKAN KURSUN, Department of Electrical & Computer Engineering, University of Rochester, Rochester, New York 14627-0231, USA. PROFESSOR DR EBY G. FRIEDMAN, Department of Electrical & Computer Engineering , University of Rochester , Rochester, New York 14627-0231, USA.

• About the Authors xiPreface xiiiAcknowledgments xvChapter 1 Introduction 11.1 Evolution of Integrated Circuits 31.2 Outline of the Book 14Chapter 2 Sources of Power Consumption in CMOS ICs 192.1 Dynamic Switching Power 192.2 Leakage Power 222.2.1 Subthreshold Leakage Current 222.2.1.1 Short-Channel Effects 232.2.1.2 Drain-Induced Barrier-Lowering 252.2.1.3 Characterization of Subthreshold Leakage Current 252.2.2 Gate Oxide Leakage Current 282.2.2.1 Effect of Technology Scaling on Gate Oxide Leakage 292.2.2.2 Characterization of Gate Oxide Leakage Current 322.2.2.3 Alternative Gate Dielectric Materials 382.3 Short-Circuit Power 392.4 Static DC Power 43Chapter 3 Supply and Threshold Voltage Scaling Techniques 453.1 Dynamic Supply Voltage Scaling 483.2 Multiple Supply Voltage CMOS 513.3 Threshold Voltage Scaling 543.3.1 Body Bias Techniques 583.3.1.1 Reverse Body Bias 583.3.1.2 Forward Body Bias 643.3.1.3 Bidirectional Body Bias 713.3.2 Multiple Threshold Voltage CMOS 743.4 Multiple Supply and Threshold Voltage CMOS 773.5 Dynamic Supply and Threshold Voltage Scaling 803.6 Circuits with Multiple Voltage and Clock Domains 813.7 Summary 83Chapter 4 Low-Voltage Power Supplies 854.1 Linear DC–DC Converters 874.2 Switched-Capacitor DC–DC Converters 904.3 Switching DC–DC Converters 914.3.1 Operation of a Buck Converter 924.3.2 Power Reduction Techniques for Switching DC–DC Converters 954.4 Summary 95Chapter 5 Buck Converters for On-Chip Integration 995.1 Circuit Model of a Buck Converter 1015.1.1 MOSFET-Related Power Losses 1015.1.2 Filter Inductor-Related Power Losses 1035.1.3 Filter Capacitor-Related Power Losses 1035.1.4 Total Power Consumption of a Buck Converter 1045.2 Efficiency Analysis of a Buck Converter 1045.2.1 Circuit Analysis for Global Maximum Efficiency 1055.2.2 Circuit Analysis with Limited Filter Capacitance 1085.2.3 Output Voltage Ripple Constraint 1095.3 Simulation Results 1095.4 Summary 112Chapter 6 Low-Voltage Swing Monolithic DC–DC Conversion 1156.1 Circuit Model of a Low-Voltage Swing Buck Converter 1166.1.1 MOSFET Power Dissipation 1186.1.2 MOSFET Model 1196.1.3 Filter Inductor Power Dissipation 1206.2 Low-Voltage Swing Buck Converter Analysis 1216.2.1 Full Swing Circuit Analysis for Global Maximum Efficiency 1216.2.2 Low Swing Circuit Analysis for Global Maximum Efficiency 1236.3 Summary 126Chapter 7 High Input Voltage Step-Down DC–DC Converters 1277.1 Cascode Bridge Circuits 1297.1.1 Cascode Bridge Circuit for Input Voltages up to 2Vmax 1297.1.2 Cascode Bridge Circuit for Input Voltages up to 3Vmax 1307.1.3 Cascode Bridge Circuit for Input Voltages up to 4Vmax 1327.2 High Input Voltage Monolithic Switching DC–DC Converters 1337.2.1 Operation of Cascode DC–DC Converters 1337.2.2 Efficiency Characteristics of DC–DC Converters Operating at Input Voltages up to 2Vmax 1367.2.3 Efficiency Characteristics of DC–DC Converters Operating at Input Voltages up to 3Vmax 1377.3 Summary 138Chapter 8 Signal Transfer in ICs with Multiple Supply Voltages 1398.1 A High-Speed and Low-Power Voltage Interface Circuit 1408.2 Voltage Interface Circuit Simulation Results 1418.3 Experimental Results 1448.4 Summary 146Chapter 9 Domino Logic with Variable Threshold Voltage Keeper 1479.1 Standard Domino (SD) Logic Circuits 1489.1.1 Operation of Standard Domino Logic Circuits 1489.1.2 Noise Immunity, Delay, and Energy Tradeoffs 1509.2 Domino Logic with Variable Threshold Voltage Keeper (DVTVK) 1539.2.1 Variable Threshold Voltage Keeper 1539.2.2 Dynamic Body Bias Generator 1559.3 Simulation Results 1569.3.1 Multiple-Output Domino Carry Generator with Variable Threshold Voltage Keeper 1569.3.1.1 Improved Delay and Power Characteristics with Comparable Noise Immunity 1589.3.1.2 Improved Noise Immunity with Comparable Delay or Power Characteristics 1609.3.2 Clock-Delayed Domino Logic with Variable Threshold Voltage Keeper 1619.3.3 Energy Overhead of the Dynamic Body Bias Generator 1639.4 Domino Logic with Forward and Reverse Body Biased Keeper 1649.4.1 Clock-Delayed Domino Logic with Forward and Reverse Body Biased Keeper 1659.4.2 Technology Scaling Characteristics of the Reverse and Forward Body Bias Techniques Applied to a Keeper Transistor 1689.5 Summary 169Chapter 10 Subthreshold Leakage Current Characteristics of Dynamic Circuits 17110.1 State-Dependent Subthreshold Leakage Current Characteristics 17210.2 Noise Immunity 17710.3 Power and Delay Characteristics in the Active Mode 18010.4 Dual Threshold Voltage CMOS Technology 18210.5 Summary 186Chapter 11 Sleep Switch Dual Threshold Voltage Domino Logic 18711.1 Existing Sleep Mode Circuit Techniques 18811.2 Dual Threshold Voltage Domino Logic Employing Sleep Switches 19011.3 Simulation Results 19111.3.1 Subthreshold Leakage Energy Reduction 19311.3.2 Stack Effect in Domino Logic Circuits 19411.3.3 Delay and Power Reduction in the Active Mode 19711.3.4 Sleep/Wake-Up Delay and Energy Overhead 19711.4 Noise Immunity Compensation 20011.5 Summary 204Chapter 12 Conclusions 205Bibliography 211Index 221