Formal Semantics for VHDL

Inbunden, Engelska, 1995

Av Carlos D. Kloos, Carlos Delgado Kloos, P. Breuer

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It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. This text puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism. Two chapters use Petri nets as target language and two of them higher order logic. Two use functional concepts and finally another uses the concept of evolving algebras. "Formal Semantics for VHDL" is intended for researchers in formal methods and can be used as a text for an advanced course on the subject.

Produktinformation

Utgivningsdatum1995-02-28
Mått155 x 235 x 16 mm
Vikt553 g
FormatInbunden
SpråkEngelska
SerieSpringer International Series in Engineering and Computer Science
Antal sidor249
Upplaga1995
FörlagKluwer Academic Publishers
ISBN9780792395522

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0 Giving Semantics to VHDL: An Introduction.- 1 VHDL.- 2 Semantics.- 3 A Running Example.- 4 Contents of this book.- 1 A Functional Semantics for Delta-Delay VHDL Based on Focus.- 1 Introduction.- 2 A Motivating Example.- 3 Assumptions.- 4 Formal Semantics for ?-VHDL.- 5 Conclusion.- Appendix A Syntax of ?-VHDL.- 2 A Functional Semantics for Unit-Delay VHDL.- 1 Introduction.- 2 The VHDL Subset.- 3 Functional Semantics.- 4 Summary and Future Work.- Appendix A Auxiliary Function Definitions.- 3 An Operational Semantics for a Subset of VHDL.- 1 Introduction.- 2 Related Research.- 3 Syntax.- 4 Operational Semantics.- 5 Information Organization.- 6 Rules of the Semantics.- 7 Equivalence.- 8 A NAND Gate.- 9 Conclusions.- 4 A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines.- 1 Introduction.- 2 Related Work.- 3 EA-Machines.- 4 The Formal Model.- 5 Example.- 6 Conclusion & Future Directions.- Appendix A Elaborated Example.- 5 A Formal Model of VHDL Using Coloured Petri Nets.- 1 Introduction.- 2 VHDL Event-Driven Simulation.- 3 The VHDL Execution Model.- 4 Variables, Types and Expressions.- 5 Statements, Subprograms and Processes.- 6 Implementation of a CPN Model Generator.- 7 Conclusions.- 6 A Deterministic Finite-State Model for VHDL.- 1 Introduction.- 2 Generation of the Finite-State Model.- 3 Conclusion.- Appendix A Elaborated Running Example.- Appendix B Utility Functions.- 7 A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL.- 1 Introduction.- 2 Flow Graph Model.- 3 Semantics of VHDL.- 4 The Example.- 5 Verification.- 6 Conclusion and Future Work.- References.