This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques.

Produktinformation

Utgivningsdatum2022-11-02
Mått155 x 235 x 34 mm
Vikt943 g
FormatHäftad
SpråkEngelska
Antal sidor604
Upplaga2
FörlagSpringer Verlag, Singapore
ISBN9789811632013

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Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.