Digital Electronics 3

Tertulien Ndjountche received a PhD degree in electrical engineering from Erlangen-Nuremberg University in Germany. He has worked as a professor and researcher at universities in Germany and Canada. He has published numerous technical papers and books in his fields of interest.

• Preface ixChapter 1. Synchronous Finite State Machines  11.1. Introduction  11.2. State diagram  21.3. Design of synchronous finite state machines  61.4. Examples  71.4.1. Flip-flops  71.4.2. Binary sequence detector 121.4.3. State machine implementation based on a state table 211.4.4. Variable width pulse generator  221.5. Equivalent states and minimization of the number of states  271.5.1. Implication table method 281.5.2. Partitioning method  371.5.3. Simplification of incompletely specified machines 421.6. State encoding 551.7. Transformation of Moore and Mealy state machines  611.8. Splitting finite state machines  631.8.1. Rules for splitting 631.8.2. Example 1 641.8.3. Example 2 671.9. Sequence detector implementation based on a programmable circuit  681.10. Practical considerations 701.10.1. Propagation delays and race conditions . 721.10.2. Timing specifications  741.11. Exercises 791.12. Solutions 97Chapter 2. Algorithmic State Machines  1692.1. Introduction  1692.2. Structure of an ASM 1692.3. ASM chart 1702.4. Applications  1752.4.1. Serial adder/subtracter  1752.4.2. Multiplier based on addition and shift operations 1832.4.3. Divider based on subtraction and shift operations 1872.4.4. Controller for an automatic vending machine  1892.4.5. Traffic light controller 1932.5. Exercises  2002.6. Solutions  205Chapter 3. Asynchronous Finite State Machines  2133.1. Introduction  2133.2. Overview  2143.3. Gated D latch  2143.4. Muller C-element 2183.5. Self-timed circuit 2203.6. Encoding the states of an asynchronous state machine 2243.7. Synthesis of asynchronous circuits  2273.7.1. Oscillatory cycle  2273.7.2. Essential and d-trio hazards 2283.7.3. Design of asynchronous state machines 2393.8. Application examples of asynchronous state machines  2403.8.1. Pulse synchronizer 2403.8.2. Asynchronous counter  2433.9. Implementation of asynchronous machines using SR latches or C-elements 2473.10. Asynchronous state machine operating in pulse mode  2513.11. Asynchronous state machine operating in burst mode  2563.12. Exercises 2583.13. Solutions 266Appendix. Overview of VHDL Language 287A.1. Introduction  287A.2. Principles of VHDL  287A.2.1. Names 288A.2.2. Comments 288A.2.3. Library and packages 289A.2.4. Ports  289A.2.5. Signal and variable  289A.2.6. Data types and objects  289A.2.7. Attributes 290A.2.8. Entity and architecture  291A.3. Concurrent instructions  292A.3.1. Concurrent instructions with selective assignment  293A.3.2. Concurrent instructions with conditional assignment 293A.4. Components  294A.4.1. Generics  296A.4.2. The GENERATE Instruction  296A.4.3. Process 297A.5. Sequential structures 298A.5.1. The IF instruction 298A.5.2. CASE instruction 303A.6. Testbench 306Bibliography 311Index  313