Digital Design

M. Morris Mano is an Emeritus Professor of Computer Engineering at the California State University, Los Angeles. His notable works include the Mano Machine, i.e. a theoretical computer that contains a central processing unit, random access memory, and an input-output bus. M. Morris Mano has authored numerous books in the area of digital circuits that are known for teaching the basic concepts of digital logic circuits in a clear, accessible manner. His books for the introductory digital design course, Logic and Computer Design Fundamentals and Digital Design, continue to be two of the most widely used texts around the world.Michael Ciletti is an Emeritus Professor of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. An early advocate of including HDL-based design methodology in the curriculum, he pioneered and developed the offering of several courses using Verilog, VHDL, FPGAs and standard cell based hardware implementations for design, testing, and synthesis of VLSI devices. His consulting work has ranged from processor design to providing expert witness testimony in cases involving HDLs. He has developed and presented courses for industry in The United States, Asia, and Europe. His widely-adopted textbooks have promoted the use of the now-standard Verilog HDL and encouraged adoption of HDL-based design practice in logic design and computer science curricula. Ciletti resides in Colorado Springs, CO, where he pursues a strong interest in landscape photography.

• Preface1 Digital Systems and Binary Numbers1.1 Digital Systems1.2 Binary Numbers1.3 NumberBase Conversions1.4 Octal and Hexadecimal Numbers1.5 Complements of Numbers1.6 Signed Binary Numbers1.7 Binary Codes1.8 Binary Storage and Registers1.9 Binary Logic2 Boolean Algebra and Logic Gates2.1 Introduction2.2 Basic Definitions2.3 Axiomatic Definition of Boolean Algebra2.4 Basic Theorems and Properties of Boolean Algebra2.5 Boolean Functions2.6 Canonical and Standard Forms2.7 Other Logic Operations2.8 Digital Logic Gates2.9 Integrated Circuits3 GateLevel Minimization3.1 Introduction3.2 The Map Method3.3 FourVariable K-Map3.4 ProductofSums Simplification3.5 Don’tCare Conditions3.6 NAND and NOR Implementation3.7 Other TwoLevel Implementations3.8 ExclusiveOR Function3.9 Hardware Description Languages (HDLs)4 Combinational Logic4.1 Introduction4.2 Combinational Circuits4.3 Analysis of Combinational Circuits4.4 Design Procedure4.5 Binary Adder—Subtractor4.6 Decimal Adder4.7 Binary Multiplier4.8 Magnitude Comparator4.9 Decoders4.10 Encoders4.11 Multiplexers4.12 HDL Models of Combinational Circuits5 Synchronous Sequential Logic5.1 Introduction5.2 Sequential Circuits5.3 Storage Elements: Latches5.4 Storage Elements: FlipFlops5.5 Analysis of Clocked Sequential Circuits5.6 Synthesizable HDL Models of Sequential Circuits5.7 State Reduction and Assignment5.8 Design Procedure6 Registers and Counters6.1 Registers6.2 Shift Registers6.3 Ripple Counters6.4 Synchronous Counters6.5 Other Counters6.6 HDL Models of Registers and Counters7 Memory and Programmable Logic7.1 Introduction7.2 RandomAccess Memory7.3 Memory Decoding7.4 Error Detection and Correction7.5 ReadOnly Memory7.6 Programmable Logic Array7.7 Programmable Array Logic7.8 Sequential Programmable Devices8 Design at the Register Transfer Level8.1 Introduction8.2 Register Transfer Level (RTL) Notation8.3 RTL descriptions VERILOG (Edge- and Level-Sensitive Behaviors)8.4 Algorithmic State Machines (ASMs)8.5 Design Example (ASMD Chart)8.6 HDL Description of Design Example8.7 Sequential Binary Multiplier8.8 Control Logic8.9 HDL Description of Binary Multiplier8.10 Design with Multiplexers8.11 RaceFree Design (Software Race Conditions)8.12 LatchFree Design (Why Waste Silicon?)8.13 System Verilog–An Introduction9 Laboratory Experiments with Standard ICs and FPGAs9.1 Introduction to Experiments9.2 Experiment 1: Binary and Decimal Numbers9.3 Experiment 2: Digital Logic Gates9.4 Experiment 3: Simplification of Boolean Functions9.5 Experiment 4: Combinational Circuits9.6 Experiment 5: Code Converters9.7 Experiment 6: Design with Multiplexers9.8 Experiment 7: Adders and Subtractors9.9 Experiment 8: FlipFlops9.10 Experiment 9: Sequential Circuits9.11 Experiment 10: Counters9.12 Experiment 11: Shift Registers9.13 Experiment 12: Serial Addition9.14 Experiment 13: Memory Unit9.15 Experiment 14: Lamp Handball9.16 Experiment 15: ClockPulse Generator9.17 Experiment 16: Parallel Adder and Accumulator9.18 Experiment 17: Binary Multiplier9.19 HDL Simulation Experiments and Rapid Prototyping with FPGAs10 Standard Graphic Symbols10.1 RectangularShape Symbols10.2 Qualifying Symbols10.3 Dependency Notation10.4 Symbols for Combinational Elements10.5 Symbols for FlipFlops10.6 Symbols for Registers10.7 Symbols for Counters10.8 Symbol for RAMAppendixAnswers to Selected ProblemsIndex