Computer Architecture

Inbunden, Engelska, 2012

Av Gérard Blanchet, Bertrand Dupouy, France) Blanchet, Gerard (Telecom ParisTech, France) Dupouy, Bertrand (Telecom ParisTech

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This book lays out the concepts necessary to understand how a computer works.For reasons of clarity, the authors have deliberately chosen examples that apply to machines from all eras, without having to water down the contents of the book. This choice helps to show how techniques, concepts and performances have evolved since the first computers.The book is divided into five parts. The first four, which are of increasing difficulty, are the core of the book: “Elements of a Basic Architecture”, “Programming Model and Operation”, “Memory Hierarchy”, “Parallelism and Performance Enhancement”. The final part provides hints and solutions to the exercises in the book as well as appendices. The reader may approach each part independently based on their prior knowledge and goals.

Produktinformation

Utgivningsdatum2012-12-18
Mått161 x 240 x 27 mm
Vikt708 g
FormatInbunden
SpråkEngelska
Antal sidor380
FörlagISTE Ltd and John Wiley & Sons Inc
ISBN9781848214293

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Preface xiii Part 1. Elements of a Basic Architecture 1 Chapter 1. Introduction 3 1.1. Historical background 3 1.2. Introduction to internal operation 13 1.3. Future prospects 15Chapter 2. The Basic Module 172.1. Memory 17 2.2. The processor 20 2.3. Communication between modules 30Chapter 3. The Representation of Information 35 3.1 Review 36 3.2. Number representation conventions 38 3.3. Character representation 48 3.4 Exercises 52Part 2. Programming Model and Operations 55Chapter 4. Instructions 57 4.1. Programming model 58 4.2 The set of instructions 62 4.3. Programming examples 68 4.4. From assembly language to basic instructions 70Chapter 5. The Processor 74 5.1. The control bus 76 5.2. Execution of the instruction 79 5.3. Sequencer composition 87 5.4. Extensions 91 5.5. Exercise 101Chapter 6. Inputs and Outputs 103 6.1. Examples 105 6.2. Design and addressing of EU 115 6.3. Exchange modes 118 6.4. Handling interrupts 127 6.5. Exercises 133Part 3. Memory Hierarchy 137Chapter 7. Memory 139 7.1. The memory resource 139 7.2. Characteristics 140 7.3. Memory hierarchy 141 7.4. Memory size and protection 145 7.5. Segmentation 145 7.6. Paging 148 7.7. Memory interleaving and burst mode 151 7.8. Protections, example of the I386 154Chapter 8. Caches 157 8.1. Cache memory 157 8.2. Replacements algorithms 165Chapter 9. Virtual Memory 175 9.1. General concept 176 9.2. Rules of the access method 178 9.3 Example of the execution of a program 182 9.4. Example of two-level paging 188 9.5 Paged segmentation 194 9.6. Exercise 197 9.7. Documentation excerpts 198Part 4. Parallelism and Performance Enhancement 205Chapter 10. Pipeline Architectures 207 10.1 Motivations and Ideas 207 10.2 Pipeline management problems 212 10.3 Handling branches 218 10.4 Interrupts and exceptions 233Chapter 11. Example of an Architecture 235 11.1 Presentation 235 11.2. Executing an instruction 240 11.3. Conflict resolution in the DLX 246 11.4. Exercises 252Chapter 12. Caches in a Multiprocessor Environment 261 12.1. Cache coherence 262 12.2. Examples of snooping protocols 267 12.3. Improvements 275 12.4. Directory-based coherence protocols 275 12.5. Consistency 278 12.6. Exercises 284Chapter 13. Superscaler Architectures 287 13.1. Superscaler architecture principles 287 13.2. Seeking solutions 290 13.3. Handling the flow of instructions 295 13.4. VLIW architectures 315 13.5. Exercises 321Part 5. Appendices 325Appendix A. Hints and Solutions 327 A1.1 The representation of information 327 A1.2. The processor 330 A1.3. Inputs and outputs 331 A1.4. Virtual memory 333 A1.5. Pipeline architectures 335 A1.6. Caches in a multiprocessor environment 341 A1.7. Superscaler architectures 344Appendix B. Programming Models 347 A2.1. Instruction coding in the I8086 347 A2.2. Instruction set of the DLX architecture 349Bibliography 351 Index 357