CAD of Circuits and Integrated Systems

Inbunden, Engelska, 2020

AvAli Mahdoum,Algeria) Mahdoum, Ali (Universite Saad Dahlab de Blida

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This book addresses the difficulty of obtaining a quality solution, that is, pre optimal or even optimal, in a reasonable time from a central processing unit (CPU). As polynomial problems can be treated by exact methods, the problem posed concerns non-polynomial problems, for which it is necessary to develop efficient algorithms based on heuristics or meta-heuristics. Chapter 3 of this book demonstrates how to develop such algorithms, which are characterized by: an initialization of argued solutions (sometimes, the global optimum can be obtained from such an initialization); a non-random generation of solutions (to avoid generating the same solution several times, or even generating solutions that cannot be achieved); avoidance of being trapped by a local optimum; good use of CPU time by reducing the size of the space of solutions to be explored (which is often very large for such problems) without compromising the quality of the solution; plus a reasoned displacement from one solution to another, to improve the quality of the solution as the processing is carried out. These aspects are applied to concrete applications in the design of integrated circuits and systems at various levels. To do this and to help the reader better understand this problem, Chapters 1 and 2 present basic notions on computational complexity, and the design of integrated circuits and systems.

Produktinformation

Utgivningsdatum2020-07-31
Mått160 x 236 x 23 mm
Vikt590 g
FormatInbunden
SpråkEngelska
Antal sidor288
FörlagISTE Ltd and John Wiley & Sons Inc
ISBN9781786305978

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Preface ixChapter 1. Basic Notions on Computational Complexity and Approximate Techniques 11.1. Computational complexity 11.1.1. Introduction 11.1.2. Big O notation 21.1.3. Ω Notation 31.1.4. Calculation of T(n) 41.2. Language computability 101.2.1. Turing machine and class P 101.2.2. Non-deterministic algorithm and class NP 121.2.3. NP-complete problems 161.2.4. NP-hard problems 271.2.5. NP-intermediate problems 311.2.6. Co-NP problems 331.2.7. Class hierarchy 341.3. Heuristics and metaheuristics 351.3.1. Definitions 351.3.2. Graph theory 361.3.3. Branch and bound technique 371.3.4. Tabu search technique 411.3.5. Simulated annealing technique 431.3.6. Genetic and evolutionary algorithms 451.4. Conclusion 48Chapter 2. Basic Notions on the Design of Digital Circuits and Systems 492.1. Introduction 492.2. History of VLSI circuit design 492.2.1. Prediffused circuit 492.2.2. Sea of gates 492.2.3. Field-programmable gate array – FPGA 512.2.4. Elementary pre-characterized circuit (standard cells) 522.2.5. Full-custom circuit 532.2.6. Silicon compilation 542.3. System design level 572.3.1. Synthesis 572.3.2. Floorplanning 642.3.3. Analysis 652.3.4. Verification 662.4. Register transfer design level 692.4.1. Synthesis 692.4.2. Analysis 902.4.3. Verification 912.5. Module design level 922.5.1. Synthesis 922.5.2. Analysis 932.5.3. Verification 982.6. Gate design level 992.6.1. Synthesis 992.6.2. Analysis 1112.6.3. Verification 1122.7. Transistor level 1122.7.1. NMOS and CMOS technologies 1122.7.2. Theory of MOS transistor (current IDS) 1142.7.3. Transfer characteristics of the inverter 1172.7.4. Static analysis of the inverter 1182.7.5. Threshold voltage of the inverter 1192.7.6. Estimation of the rise and fall times of a capacitor 1202.8. Interconnections 1242.8.1. Synthesis of interconnections 1262.8.2. Synthesis of networks-on-chip 1402.9. Conclusion 151Chapter 3. Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems 1533.1. Introduction 1533.2. System level 1543.2.1. Synthesis of systems-on-chip (SoCs) with low energy consumption 1543.2.2. Heuristic application to dynamic voltage and frequency scaling (DVFS) for the design of a real-time system subject to energy constraint 1603.3. Register transfer level 1743.3.1. Integer linear programming applied to the scheduling of operations of a data flow graph (DFG) 1743.3.2. The scheduling of operations in a controlled data flow graph (considering the speed–power consumption tradeoff) 1763.3.3. Efficient code assignment to the states of a finite state machine (aimed at reaching an effective control part in terms of surface, speed and power consumption) 1763.3.4. Synthesis of submicron transistors and interconnections for the design of high-performance (low-power) circuits subject to power (respectively time) and surface constraints 1963.4. Module level 2073.4.1. Design of low-power digital circuits 2073.4.2. Reduction of memory access time for the design of embedded systems 2193.5. Gate level 2273.5.1. Estimation of the average and maximal power consumption of a digital circuit 2273.5.2. Automated layout generation of some regular structures (shifters, address decoders, PLAs) 2343.5.3. Automated layout generation of digital circuits according to the River PLA technique 2383.6. Interconnections 2393.6.1. Low-power buffer insertion technique for the design of submicron interconnections with delay and surface constraints 2393.6.2. Data encoding and decoding for low-power aided design of submicron interconnections 2503.6.3. High-level synthesis of networks-on-chip subject to bandwidth, surface and power consumption constraints 2533.7. Conclusion 263References 267Index 273