Analog Integrated Circuit Design, International Student Version

Häftad, Engelska, 2012

AvTony Chan Carusone,David A. Johns,Kenneth W. Martin,Canada) Carusone, Tony Chan (University of Toronto,Canada) Johns, David A. (University of Toronto,Canada) Martin, Kenneth W. (University of Toronto

809 kr

Beställningsvara. Skickas inom 7-10 vardagar. Fri frakt för medlemmar vid köp för minst 249 kr.

When first published this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated but continues the central themes of the first edition which made it so sucessful.This edition features extensive new material on CMOS IC device modeling, processing and layout. Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A/D converters. Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers.

Produktinformation

Utgivningsdatum2012-05-11
Mått191 x 236 x 26 mm
Vikt1 198 g
FormatHäftad
SpråkEngelska
Antal sidor832
Upplaga2
FörlagJohn Wiley & Sons Inc
ISBN9781118092330

Tillhör följande kategorier

Elektronik och kommunikationer inom Naturvetenskap och teknik

CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING 11.1 Semiconductors and pn Junctions 11.1.1 Diodes 21.1.2 Reverse-Biased Diodes 41.1.3 Graded Junctions 81.1.4 Large-Signal Junction Capacitance 101.1.5 Forward-Biased Junctions 111.1.6 Junction Capacitance of Forward-Biased Diode 121.1.7 Small-Signal Model of a Forward-Biased Diode 131.1.8 Schottky Diodes 141.2 MOS Transistors 151.2.1 Symbols for MOS Transistors 161.2.2 Basic Operation 171.2.3 Large-Signal Modelling 221.2.4 Body Effect 251.2.5 p-Channel Transistors 261.2.6 Low-Frequency Small-Signal Modelling in the Active Region 261.2.7 High-Frequency Small-Signal Modelling in the Active Region 321.2.8 Small-Signal Modelling in the Triode and Cutoff Regions 351.2.9 Analog Figures of Merit and Trade-offs 371.3 Device Model Summary 391.3.1 Constants 401.3.2 Diode Equations 401.3.3 MOS Transistor Equations 411.4 Advanced MOS Modelling 431.4.1 Subthreshold Operation 431.4.2 Mobility Degradation 461.4.3 Summary of Subthreshold and Mobility Degradation Equations 481.4.4 Parasitic Resistances 481.4.5 Short-Channel Effects 491.4.6 Leakage Currents 501.5 SPICE Modelling Parameters 511.5.1 Diode Model 511.5.2 MOS Transistors 521.5.3 Advanced SPICE Models of MOS Transistors 521.6 Passive Devices 551.6.1 Resistors 551.6.2 Capacitors 591.7 Appendix 611.7.1 Diode Exponential Relationship 611.7.2 Diode-Diffusion Capacitance 631.7.3 MOS Threshold Voltage and the Body Effect 651.7.4 MOS Triode Relationship 671.8 Key Points 691.9 References 701.10 Problems 70CHAPTER 2 PROCESSING AND LAYOUT 732.1 CMOS Processing 732.1.1 The Silicon Wafer 732.1.2 Photolithography and Well Definition 742.1.3 Diffusion and Ion Implantation 762.1.4 Chemical Vapor Deposition and Defining the Active Regions 782.1.5 Transistor Isolation 782.1.6 Gate-Oxide and Threshold-Voltage Adjustments 812.1.7 Polysilicon Gate Formation 822.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes 822.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition 842.1.10 Additional Processing Steps 842.2 CMOS Layout and Design Rules 862.2.1 Spacing Rules 862.2.2 Planarity and Fill Requirements 942.2.3 Antenna Rules 942.2.4 Latch-Up 952.3 Variability and Mismatch 962.3.1 Systematic Variations Including Proximity Effects 962.3.2 Process Variations 982.3.3 Random Variations and Mismatch 992.4 Analog Layout Considerations 1032.4.1 Transistor Layouts 1032.4.2 Capacitor Matching 1042.4.3 Resistor Layout 1072.4.4 Noise Considerations 1092.5 Key Points 1122.6 References 1132.7 Problems 114CHAPTER 3 BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS 1173.1 Simple CMOS Current Mirror 1183.2 Common-Source Amplifier 1203.3 Source-Follower or Common-Drain Amplifier 1223.4 Common-Gate Amplifier 1243.5 Source-Degenerated Current Mirrors 1273.6 Cascode Current Mirrors 1293.7 Cascode Gain Stage 1313.8 MOS Differential Pair and Gain Stage 1353.9 Key Points 1383.10 References 1393.11 Problems 139CHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS 1444.1 Frequency Response of Linear Systems 1444.1.1 Magnitude and Phase Response 1454.1.2 First-Order Circuits 1474.1.3 Second-Order Low-Pass Transfer Functions with Real Poles 1544.1.4 Bode Plots 1574.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles 1634.2 Frequency Response of Elementary Transistor Circuits 1644.2.1 High-Frequency MOS Small-Signal Model 1644.2.2 Common-Source Amplifier 1664.2.3 Miller Theorem and Miller Effect 1694.2.4 Zero-Value Time-Constant Analysis 1734.2.5 Common-Source Design Examples 1764.2.6 Common-Gate Amplifier 1794.3 Cascode Gain Stage 1814.4 Source-Follower Amplifier 1874.5 Differential Pair 1934.5.1 High-Frequency T Model 1934.5.2 Symmetric Differential Amplifier 1944.5.3 Single-Ended Differential Amplifier 1954.5.4 Differential Pair with Active Load 1964.6 Key Points 1974.7 References 1984.8 Problems 198CHAPTER 5 FEEDBACK AMPLIFIERS 2045.1 Ideal Model of Negative Feedback 2045.1.1 Basic Definitions 2045.1.2 Gain Sensitivity 2055.1.3 Bandwidth 2065.1.4 Linearity 2075.1.5 Summary 2075.2 Dynamic Response of Feedback Amplifiers 2085.2.1 Stability Criteria 2095.2.2 Phase Margin 2115.3 First- and Second-Order Feedback Systems 2135.3.1 First-Order Feedback Systems 2135.3.2 Second-Order Feedback Systems 2175.3.3 Higher-Order Feedback Systems 2205.4 Common Feedback Amplifiers 2215.4.1 Obtaining the Loop Gain, L(s) 2225.4.2 Noninverting Amplifier 2265.4.3 Transimpedance (Inverting) Amplifiers 2315.5 Summary of Key Points 2355.6 References 2365.7 Problems 236CHAPTER 6 BASIC OPAMP DESIGN AND COMPENSATION 2426.1 Two-Stage CMOS Opamp 2426.1.1 Opamp Gain 2436.1.2 Frequency Response 2456.1.3 Slew Rate 2496.1.4 n-Channel or p-Channel Input Stage 2526.1.5 Systematic Offset Voltage 2536.2 Opamp Compensation 2546.2.1 Dominant-Pole Compensation and Lead Compensation 2556.2.2 Compensating the Two-Stage Opamp 2566.2.3 Making Compensation Independent of Process and Temperature 2606.3 Advanced Current Mirrors 2626.3.1 Wide-Swing Current Mirrors 2626.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting 2636.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance 2666.3.4 Current-Mirror Symbol 2676.4 Folded-Cascode Opamp 2686.4.1 Small-Signal Analysis 2706.4.2 Slew Rate 2726.5 Current Mirror Opamp 2756.6 Linear Settling Time Revisited 2796.7 Fully Differential Opamps 2816.7.1 Fully Differential Folded-Cascode Opamp 2836.7.2 Alternative Fully Differential Opamps 2846.7.3 Low Supply Voltage Opamps 2866.8 Common-Mode Feedback Circuits 2886.9 Summary of Key Points 2926.10 References 2936.11 Problems 294CHAPTER 7 BIASING, REFERENCES, AND REGULATORS 3027.1 Analog Integrated Circuit Biasing 3027.1.1 Bias Circuits 3037.1.2 Reference Circuits 3057.1.3 Regulator Circuits 3067.2 Establishing Constant Transconductance 3077.2.1 Basic Constant-Transconductance Circuit 3077.2.2 Improved Constant-Transconductance Circuits 3097.3 Establishing Constant Voltages and Currents 3107.3.1 Bandgap Voltage Reference Basics 3107.3.2 Circuits for Bandgap References 3147.3.3 Low-Voltage Bandgap Reference 3197.3.4 Current Reference 3207.4 Voltage Regulation 3217.4.1 Regulator Specifications 3217.4.2 Feedback Analysis 3227.4.3 Low Dropout Regulators 3247.5 Summary of Key Points 3277.6 References 3277.7 Problems 328CHAPTER 8 BIPOLAR DEVICES AND CIRCUITS 3318.1 Bipolar-Junction Transistors 3318.1.1 Basic Operation 3318.1.2 Analog Figures of Merit 3418.2 Bipolar Device Model Summary 3448.3 SPICE Modeling 3458.4 Bipolar and BICMOS Processing 3468.4.1 Bipolar Processing 3468.4.2 Modern SiGe BiCMOS HBT Processing 3478.4.3 Mismatch in Bipolar Devices 3488.5 Bipolar Current Mirrors and Gain Stages 3498.5.1 Current Mirrors 3498.5.2 Emitter Follower 3508.5.3 Bipolar Differential Pair 3538.6 Appendix 3568.6.1 Bipolar Transistor Exponential Relationship 3568.6.2 Base Charge Storage of an Active BJT 3598.7 Summary of Key Points 3598.8 References 3608.9 Problems 360CHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING 3639.1 Time-Domain Analysis 3639.1.1 Root Mean Square (rms) Value 3649.1.2 SNR 3659.1.3 Units of dBm 3659.1.4 Noise Summation 3669.2 Frequency-Domain Analysis 3679.2.1 Noise Spectral Density 3679.2.2 White Noise 3699.2.3 1/f, or Flicker, Noise 3709.2.4 Filtered Noise 3719.2.5 Noise Bandwidth 3739.2.6 Piecewise Integration of Noise 3759.2.7 1/f Noise Tangent Principle 3779.3 Noise Models for Circuit Elements 3779.3.1 Resistors 3789.3.2 Diodes 3789.3.3 Bipolar Transistors 3809.3.4 MOSFETS 3809.3.5 Opamps 3829.3.6 Capacitors and Inductors 3829.3.7 Sampled Signal Noise 3849.3.8 Input-Referred Noise 3849.4 Noise Analysis Examples 3879.4.1 Opamp Example 3879.4.2 Bipolar Common-Emitter Example 3909.4.3 CMOS Differential Pair Example 3929.4.4 Fiber-Optic Transimpedance Amplifier Example 3959.5 Dynamic Range Performance 3979.5.1 Total Harmonic Distortion (THD) 3989.5.2 Third-Order Intercept Point (IP3) 4009.5.3 Spurious-Free Dynamic Range (SFDR) 4029.5.4 Signal-to-Noise and Distortion Ratio (SNDR) 4049.6 Key Points 4059.7 References 4069.8 Problems 406CHAPTER 10 COMPARATORS 41310.1 Comparator Specifications 41310.1.1 Input Offset and Noise 41310.1.2 Hysteresis 41410.2 Using an Opamp for a Comparator 41510.2.1 Input-Offset Voltage Errors 41710.3 Charge-Injection Errors 41810.3.1 Making Charge-Injection Signal Independent 42110.3.2 Minimizing Errors Due to Charge-Injection 42110.3.3 Speed of Multi-Stage Comparators 42410.4 Latched Comparators 42610.4.1 Latch-Mode Time Constant 42810.4.2 Latch Offset 43010.5 Examples of CMOS and BiCMOS Comparators 43210.5.1 Input-Transistor Charge Trapping 43510.6 Examples of Bipolar Comparators 43710.7 Key Points 43910.8 References 44010.9 Problems 441CHAPTER 11 SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS 44411.1 Performance of Sample-and-Hold Circuits 44411.1.1 Testing Sample-and-Holds 44511.2 MOS Sample-and-Hold Basics 44611.3 Examples of CMOS S/H Circuits 45211.4 Bipolar and BiCMOS Sample-and-Holds 45611.5 Translinear Gain Cell 46011.6 Translinear Multiplier 46211.7 Key Points 46411.8 References 46511.9 Problems 466CHAPTER 12 CONTINUOUS-TIME FILTERS 46912.1 Introduction to Continuous-Time Filters 46912.1.1 First-Order Filters 47012.1.2 Second-Order Filters 47012.2 Introduction to Gm-C Filters 47112.2.1 Integrators and Summers 47212.2.2 Fully Differential Integrators 47312.2.3 First-Order Filter 47512.2.4 Biquad Filter 47712.3 Transconductors Using Fixed Resistors 47812.4 CMOS Transconductors Using Triode Transistors 48312.4.1 Transconductors Using a Fixed-Bias Triode Transistor 48412.4.2 Transconductors Using Varying Bias-Triode Transistors 48612.4.3 Transconductors Using Constant Drain-Source Voltages 49012.5 CMOS Transconductors Using Active Transistors 49212.5.1 CMOS Pair 49312.5.2 Constant Sum of Gate-Source Voltages 49412.5.3 Source-Connected Differential Pair 49512.5.4 Inverter-Based 49512.5.5 Differential-Pair with Floating Voltage Sources 49612.5.6 Bias-Offset Cross-Coupled Differential Pairs 49912.6 Bipolar Transconductors 49912.6.1 Gain-Cell Transconductors 50012.6.2 Transconductors Using Multiple Differential Pairs 50212.7 BiCMOS Transconductors 50612.7.1 Tunable MOS in Triode 50612.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier 50712.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier 50812.8 Active RC and MOSFET-C Filters 50912.8.1 Active RC Filters 51012.8.2 MOSFET-C Two-Transistor Integrators 51212.8.3 Four-Transistor Integrators 51512.8.4 R-MOSFET-C Filters 51612.9 Tuning Circuitry 51712.9.1 Tuning Overview 51712.9.2 Constant Transconductance 51912.9.3 Frequency Tuning 52012.9.4 Q-Factor Tuning 52212.9.5 Tuning Methods Based on Adaptive Filtering 52312.10 Introduction to Complex Filters 52512.10.1 Complex Signal Processing 52512.10.2 Complex Operations 52612.10.3 Complex Filters 52712.10.4 Frequency-Translated Analog Filters 52812.11 Key Points 53112.12 References 53212.13 Problems 534CHAPTER 13 DISCRETE-TIME SIGNALS 53713.1 Overview of Some Signal Spectra 53713.2 Laplace Transforms of Discrete-Time Signals 53713.2.1 Spectra of Discrete-Time Signals 54013.3 z-Transform 54113.4 Downsampling and Upsampling 54313.5 Discrete-Time Filters 54513.5.1 Frequency Response of Discrete-Time Filters 54513.5.2 Stability of Discrete-Time Filters 54813.5.3 IIR and FIR Filters 55013.5.4 Bilinear Transform 55013.6 Sample-and-Hold Response 55213.7 Key Points 55413.8 References 55513.9 Problems 555CHAPTER 14 SWITCHED-CAPACITOR CIRCUITS 55714.1 Basic Building Blocks 55714.1.1 Opamps 55714.1.2 Capacitors 55814.1.3 Switches 55814.1.4 Nonoverlapping Clocks 55914.2 Basic Operation and Analysis 56014.2.1 Resistor Equivalence of a Switched Capacitor 56014.2.2 Parasitic-Sensitive Integrator 56314.2.3 Parasitic-Insensitive Integrators 56514.2.4 Signal-Flow-Graph Analysis 56914.3 Noise in Switched-Capacitor Circuits 57014.4 First-Order Filters 57214.4.1 Switch Sharing 57514.4.2 Fully Differential Filters 57514.5 Biquad Filters 57714.5.1 Low-Q Biquad Filter 57714.5.2 High-Q Biquad Filter 58114.6 Charge Injection 58514.7 Switched-Capacitor Gain Circuits 58814.7.1 Parallel Resistor-Capacitor Circuit 58814.7.2 Resettable Gain Circuit 58814.7.3 Capacitive-Reset Gain Circuit 59114.8 Correlated Double-Sampling Techniques 59314.9 Other Switched-Capacitor Circuits 59414.9.1 Amplitude Modulator 59414.9.2 Full-Wave Rectifier 59514.9.3 Peak Detectors 59614.9.4 Voltage-Controlled Oscillator 59614.9.5 Sinusoidal Oscillator 59814.10 Key Points 60014.11 References 60114.12 Problems 602CHAPTER 15 DATA CONVERTER FUNDAMENTALS 60615.1 Ideal D/A Converter 60615.2 Ideal A/D Converter 60815.3 Quantization Noise 60915.3.1 Deterministic Approach 60915.3.2 Stochastic Approach 61015.4 Signed Codes 61215.5 Performance Limitations 61415.5.1 Resolution 61415.5.2 Offset and Gain Error 61515.5.3 Accuracy and Linearity 61515.6 Key Points 62015.7 References 62015.8 Problems 620CHAPTER 16 NYQUIST-RATE D/A CONVERTERS 62316.1 Decoder-Based Converters 62316.1.1 Resistor-String Converters 62316.1.2 Folded Resistor-String Converters 62516.1.3 Multiple Resistor-String Converters 62616.1.4 Signed Outputs 62816.2 Binary-Scaled Converters 62916.2.1 Binary-Weighted Resistor Converters 62916.2.2 Reduced-Resistance-Ratio Ladders 63016.2.3 R-2R-Based Converters 63116.2.4 Charge-Redistribution Switched-Capacitor Converters 63216.2.5 Current-Mode Converters 63316.2.6 Glitches 63316.3 Thermometer-Code Converters 63416.3.1 Thermometer-Code Current-Mode D/A Converters 63616.3.2 Single-Supply Positive-Output Converters 63716.3.3 Dynamically Matched Current Sources 63816.4 Hybrid Converters 64016.4.1 Resistor-Capacitor Hybrid Converters 64016.4.2 Segmented Converters 64016.5 Key Points 64216.6 References 64316.7 Problems 643CHAPTER 17 NYQUIST-RATE A/D CONVERTERS 64617.1 Integrating Converters 64617.2 Successive-Approximation Converters 65017.2.1 D/A-Based Successive Approximation 65217.2.2 Charge-Redistribution A/D 65317.2.3 Resistor-Capacitor Hybrid 65817.2.4 Speed Estimate for Charge-Redistribution Converters 65917.2.5 Error Correction in Successive-Approximation Converters 66017.2.6 Multi-Bit Successive-Approximation 66217.3 Algorithmic (or Cyclic) A/D Converter 66217.3.1 Ratio-Independent Algorithmic Converter 66317.4 Pipelined A/D Converters 66717.4.1 One-Bit-Per-Stage Pipelined Converter 66717.4.2 1.5 Bit Per Stage Pipelined Converter 67017.4.3 Pipelined Converter Circuits 67317.4.4 Generalized k-Bit-Per-Stage Pipelined Converters 67317.5 Flash Converters 67417.5.1 Issues in Designing Flash A/D Converters 67517.6 Two-Step A/D Converters 67817.6.1 Two-Step Converter with Digital Error Correction 67917.7 Interpolating A/D Converters 68117.8 Folding A/D Converters 68417.9 Time-Interleaved A/D Converters 68717.10 Key Points 69017.11 References 69117.12 Problems 692CHAPTER 18 OVERSAMPLING CONVERTERS 69618.1 Oversampling without Noise Shaping 69618.1.1 Quantization Noise Modelling 69718.1.2 White Noise Assumption 69718.1.3 Oversampling Advantage 69818.1.4 The Advantage of 1-Bit D/A Converters 70018.2 Oversampling with Noise Shaping 70118.2.1 Noise-Shaped Delta-Sigma Modulator 70218.2.2 First-Order Noise Shaping 70318.2.3 Switched-Capacitor Realization of a First-Order A/D Converter 70518.2.4 Second-Order Noise Shaping 70518.2.5 Noise Transfer-Function Curves 70718.2.6 Quantization Noise Power of 1-Bit Modulators 70818.2.7 Error-Feedback Structure 70818.3 System Architectures 71018.3.1 System Architecture of Delta-Sigma A/D Converters 71018.3.2 System Architecture of Delta-Sigma D/A Converters 71218.4 Digital Decimation Filters 71318.4.1 Multi-Stage 71418.4.2 Single Stage 71618.5 Higher-Order Modulators 71718.5.1 Interpolative Architecture 71718.5.2 Multi-Stage Noise Shaping (MASH) Architecture 71818.6 Bandpass Oversampling Converters 72018.7 Practical Considerations 72118.7.1 Stability 72118.7.2 Linearity of Two-Level Converters 72218.7.3 Idle Tones 72418.7.4 Dithering 72518.7.5 Opamp Gain 72518.8 Multi-Bit Oversampling Converters 72618.8.1 Dynamic Element Matching 72618.8.2 Dynamically Matched Current Source D/A Converters 72718.8.3 Digital Calibration A/D Converter 72718.8.4 A/D with Both Multi-Bit and Single-Bit Feedback 72818.9 Third-Order A/D Design Example 72918.10 Key Points 73118.11 References 73318.12 Problems 734CHAPTER 19 PHASE-LOCKED LOOPS 73719.1 Basic Phase-Locked Loop Architecture 73719.1.1 Voltage-Controlled Oscillator 73819.1.2 Divider 73919.1.3 Phase Detector 74019.1.4 Loop Filer 74519.1.5 The PLL in Lock 74619.2 Linearized Small-Signal Analysis 74719.2.1 Second-Order PLL Model 74819.2.2 Limitations of the Second-Order Small-Signal Model 75019.2.3 PLL Design Example 75219.3 Jitter and Phase Noise 75419.3.1 Period Jitter 75819.3.2 P-Cycle Jitter 75819.3.3 Adjacent Period Jitter 75919.3.4 Other Spectral Representations of Jitter 76019.3.5 Probability Density Function of Jitter 76119.4 Electronic Oscillators 76319.4.1 Ring Oscillators 76419.4.2 LC Oscillators 76819.4.3 Phase Noise of Oscillators 77019.5 Jitter and Phase Noise in PLLS 77419.5.1 Input Phase Noise and Divider Phase Noise 77519.5.2 VCO Phase Noise 77519.5.3 Loop Filter Noise 77619.6 Key Points 77919.7 References 77919.8 Problems 780INDEX 783