System Level ESD Co-Design

Charvaka Duvvury, formerly Texas Instruments, USACharvaka Duvvury, formerly of Texas Instruments, is currently working as a technical consultant on ESD design methods and ESD qualification support. He has published over 150 technical papers and holds more than 70 patents. He is a co-founder and co-chair of the Industry Council on ESD Target Levels and has been serving as Board of Director of the ESDA since 1997 promoting university education and research in ESD technology.Harald Gossner, Intel, GermanyHarald Gossner is Senior Principal Engineer at Intel where for 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2010 he has joined Intel Mobile Communications overseeing the development of robust mobile systems. Harald has authored and co-authored more than 100 technical papers and one book in the field of ESD and device physics. He holds more than 60 patents on the same topic. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels.

• List of Contributors xiiiPreface xvAcronyms xviiAbout the Book xxi1 Introduction 1Charvaka Duvvury1.1 Definition of Co-Design 11.2 Overview of the Book 21.3 Challenges of System Level ESD Protection 21.4 Importance of System Level Protection 21.5 Industry-Wide Perception 51.6 Purpose and Motivation 81.7 Organization and Approach 81.8 Outcome for the Reader 12Acknowledgments 12References 122 Component versus System Level ESD 14Charvaka Duvvury and Harald Gossner2.1 ESD Threat in the Real World 142.1.1 ESD Control 142.1.2 ESD Failure Types 152.1.3 ESD Protection Areas 162.1.4 ESD Stress Models 172.2 Component ESD Qualification 172.2.1 Component ESD Tests 172.2.2 ESD Levels for IC Production 182.2.3 Implications for System Level ESD 202.2.4 ESD Technology Roadmap 202.3 System Level ESD Tests 212.3.1 IEC 61000-4-2 222.4 ISO 10605 292.5 IEC 61000-4-5 312.5.1 System Applications 322.5.2 Misconceptions and Miscorrelation of Component and System Level Tests 352.5.3 Hard Failures Due to IEC Testing 422.6 Soft Failures Due to IEC Testing 42Acknowledgments 43References 433 System Level Testing for ESD Susceptibility 46Michael Hopkins3.1 Introduction 463.2 Objectives of System Level Testing 473.3 Compliance to ESD Standards 473.3.1 Legal Compliance Requirements 473.3.2 Compliance to Industry Requirements 483.4 Testing for Product Reliability 483.5 Standards Requirements for System Level Testing 493.5.1 IEC 61000-4-2 493.5.2 Automotive Standards for ESD 583.5.3 Medical Standards for ESD 603.5.4 Avionics Standards for ESD 613.5.5 Military ESD Standards 613.6 Using the IEC Simulator for Device Testing 623.7 Cable Discharge (CDE) Testing 633.7.1 Shielded Cables 653.7.2 Unshielded Cables 653.7.3 Modified Transmission Line Pulsers (TLP) for CDE Testing 663.8 Evaluation of Test Results 673.8.1 Hard Failure Evaluation 673.8.2 Soft Failure Evaluation 673.9 The Quick Fix vs Root Cause Determination 673.10 Determining Root Cause of System Level ESD 683.11 Reproducibility of System Level ESD Tests 70Acknowledgments 72References 724 PCB/IC Co-Design Concepts for SEED 74Harald Gossner and Charvaka Duvvury4.1 On-Chip System ESD Protection 744.1.1 HBM and CDM vs IEC 744.1.2 TLP Characterization 764.1.3 TLP Correlation Issues 784.2 Off-Chip ESD Protection 794.3 Concept of PCB/IC Co-Design 824.3.1 On-Chip IEC Protection Solutions 844.4 Introduction to System Efficient ESD Design 844.4.1 Design Methods for SEED 904.4.2 Basic Simulations using SEED 914.4.3 USB Design using SEED 944.5 Characterization for Hard Failures 974.6 Simulation of System Level ESD Discharge Paths 984.6.1 Simulation Approach 984.6.2 Tools 1014.6.3 ESD Model Types 1034.6.4 Extraction of PCB Paths 1044.6.5 Models of PCB Devices 1044.6.6 Characterization of IO Cells 1064.6.7 Power Clamp Models 1124.6.8 Model for Stress Waveform 1144.7 Characterization of Soft Failures 1164.7.1 Purpose and Basic Concept 1164.7.2 Pin Specific Soft Failure Characterization 1204.7.3 Soft Failures Related to Signal Integrity Problems 1234.8 Summary of SEED Characterization 125Acknowledgments 126References 1275 Hard Failures and PCB Protection Devices 129Robert Ashton5.1 Introduction 1295.2 ESD Damage to ICs 1295.3 Protection Methods 1305.3.1 Classification of TVS Devices 1335.4 Characteristics of Protection Devices 1345.4.1 Current Limiting Devices 1345.4.2 TVS Properties in Their Off-State 1355.4.3 Protection Properties of TVS Devices 1375.5 Types of Protection Devices for ESD 1425.5.1 Silicon Based TVS Devices 1435.5.2 Metal Oxide Varistors 1545.5.3 Polymer Voltage Suppressors 1555.5.4 Gas Discharge Tubes 1565.5.5 Spark Gaps on PCBs 1585.5.6 Thyristor Surge Protection Devices 1595.5.7 Ferrite Beads 1595.5.8 Passive Components 1615.5.9 Common Mode Filters 1625.6 Primary and Secondary Protection 1635.7 Evaluating IC Pins 1645.8 Choosing ESD Protection Devices 1645.8.1 Coordination between TVS Device and Sensitive Nodes 1655.9 Summary 167References 1676 Soft Failure Mechanisms and PCB Design Measures 169David Pommerenke and Pratik Maheshwari6.1 Introduction 1696.2 Are HBM, CDM, MM, and Latch-Up Results Meaningful Soft Failures? 1716.3 Classification of Soft Failure Modes 1736.3.1 In-Band/Out-of-Band with Respect to Voltage 1746.3.2 In-Band/Out-of-Band with Respect to Pulse Width 1756.3.3 Local vs Distant Errors 1766.3.4 Amplified/Non-amplified Soft Failures 1766.4 Optimized System Level Testing 1786.5 Soft Failure Characterization Methods 1826.5.1 Susceptibility Scanning 1836.5.2 Current Spreading Reconstruction 1906.5.3 Local Injection 1916.5.4 Software-Based Methods for Soft Failure Analysis 2016.6 Soft Failure Examples 2056.6.1 Example 1: Soft Failure Caused by Field Injection on a DUT (Mini Photo Frame) 2056.6.2 Example 2: PLL Disturbance Measurement 2076.6.3 Example 3: Direct Field Coupling on the USB Data Bus 2126.6.4 Example 4: Direct Injection on the MIPI Bus Interface 2156.7 Countermeasure Examples 2166.7.1 Divert Current 2166.7.2 Filtering 2176.7.3 Shielding 2176.7.4 Secondary ESD Avoidance 2186.7.5 Improved Connector-Cable Shield Connection 2186.7.6 Enclosure to Connector Shield Junction 2186.7.7 Firmware 2186.7.8 Reducing Crosstalk 2196.7.9 Reduce ESD Current by Resistance 2206.7.10 Avoid ESD 2226.8 The Way Forward 223Acknowledgment 230References 2317 ESD in Mobile Devices 234Matti Uusimäki7.1 Introduction 2347.2 ESD Energy Path in Mobile Device 2347.3 ESD Generation Examples on a Large Scale 2397.3.1 Large Machines Generating Charges to Their Isolated Bodies 2397.3.2 Tribo-Electric Series 2407.3.3 Charge Generated by a Person Inside a Car 2407.3.4 The Charge Generated to Mobile Device by Accident in Grounded System 2417.3.5 Alternative Discharging Paths at Connection Moment 2447.3.6 Charge Behavior at Insulator Surface 2447.3.7 Example of Consumer Level Charge Generation with Simple Device 2467.4 Relation between Electrostatic Discharge Immunity Test and Real-World Discharge Waveforms 2487.5 Laboratory Test Methods 2487.6 Fast ESD and Slow ESD Concepts 2497.7 Fast-ESD and Slow-ESD in a Mobile Device 2507.7.1 Example of Ground Level Bounce Relative to an External Module 2517.8 Isolating a Mobile Device 2527.8.1 Example 1: Material Thickness 2527.8.2 Example 2: Solid Glue 2537.8.3 Example 3: Positioning Holes in a Rubberized Key Mat 2557.8.4 Example 4: Induced Electric Field 2557.9 Shielding a Mobile Device 2577.10 Orientation Effects on ESD Path 2597.10.1 ESD Path Example: Phone Face Up on Table 2597.10.2 ESD Path Example: Phone Face Down on the Table 2637.11 ESD Design in Practice 2647.11.1 Grounding Challenges in Practice 2647.12 PCB Layout Considerations of Metal Shielding “Cans” 2677.12.1 Components Near the Edge of the Shield 2687.13 ESD Protection for Cable Interfaces 2697.13.1 Cable Placement and Common Mode Current in a Mobile Device 2707.13.2 Localizing Noise Current with Alternate Cabling Placement 2747.13.3 Cable Interface Protection Components 2757.14 Common Mode Impedance Concerns for Layout 2807.14.1 Common Mode Impedance Challenges in the Grounding Paths 2807.14.2 Signals with Shared Common Mode Impedance 2807.14.3 Isolating Signals with Shield Grounded to Internal PCB Layers 2827.14.4 Simulated Example of Ground Impedance Effect on ESD/EMI Filter Performance 2837.14.5 ESD Protection on Stacked Chips 2837.14.6 Layout Concerns around the Periphery and PCB Cutouts 2857.15 ESD and Software Considerations in Mobile Devices 2877.15.1 Role of Software in EMC and ESD Design 2877.15.2 Signal Sensitivity to ESD Examples 2887.15.3 Delayed Effects on Software from ESD Events 2907.16 Software Versions Utilized in Early ESD Immunity Testing 2917.17 Conclusion 292References 2928 ESD for Automotive Applications 294Wolfgang Reinprecht8.1 Introduction and Historical Aspects 2948.1.1 Why Do Automotive Components Require High ESD Levels? 2948.1.2 Field Return Rate of Automotive Products due to System Level ESD Events 2968.1.3 ESD Related Field Returns Because of Incomplete Specification or Missing System Protection 2978.2 Automotive Components 2998.2.1 Communication Systems CAN, LIN, FlexRay 2998.2.2 Power Supply Systems as DCDC Converter, Alternator, LDO 3038.2.3 Sensors and Sensor Interfaces 3048.2.4 Keyless Entry/Go with Components Exposed to Human Touching/Handling 3118.2.5 Power Steering, Drive by Wire, Gearbox, Hybrid Systems, Recuperation 3138.2.6 LED Lights, Entertainment, Navigation, and Audio 3138.3 Design Constraints, Operating Voltage, and Overvoltage Tolerance 3158.3.1 “Normal Overvoltage Range”: 18 V into 5 V/3 V/1.8 V 3158.3.2 Load Dump 3158.3.3 Loss of Ground, Dual Polarity, and Reverse Polarity 3178.3.4 EMC Tolerance versus ESD Robustness (Fast Transients) 3198.3.5 Leakage Current versus ESD Robustness (Pre-Pulse Voltage) 3208.3.6 Latch-Up-Free ESD Protection versus Snapback Devices 3218.4 On-Board ESD Protection and Internal ESD Protection 3248.4.1 Characterization Methods to Get Relevant Data for External ESD Devices 3248.4.2 ESD Design Window Using External Protection Elements (TVS) 3248.4.3 Optimizing On-Chip ESD Protections to Match Board Level Protection 3248.4.4 On-Board Ground Shift due to System ESD Events 3258.4.5 Secondary Effects as Transient Disturbances to “Internal” Pins (Lateral Coupling) 3268.4.6 Pin Placement, External Passive Components, and Board Layout Constraints 3288.5 Verification and Qualification 3298.5.1 Safe Operating Area Check to Verify Overvoltage Tolerance 3298.5.2 ESD Design Rule Check to Verify ESD Concept and Constraints 3308.5.3 ESD Tests on Chip Level HBM/CDM 3318.5.4 TLP Characterization of Product to Meet SEED 3318.5.5 System ESD Tests on Board Level up to the Level of Failure 3318.5.6 No-Gos in Terms of ESD Design 3328.6 Conclusion 332References 3339 Future Applications of SEED Methodology 334Harald Gossner and Charvaka Duvvury9.1 Refinement of Models 3349.2 Limitations of Simulation and Beyond 3379.2.1 Relation of SEED to System ESD Tests 3379.2.2 Outlook to a Comprehensive Design Verification 3419.3 Advances toward High-Speed Systems 3429.3.1 USB and HDMI Challenges 3439.4 Issues and Challenges of System Protection 3459.4.1 USB 2.0 versus USB 3.0 3459.4.2 USB 2.0/3.0 versus HDMI 3469.4.3 Automotive Technologies 3469.4.4 IC Package Technologies 3479.4.5 PCB Technologies 3479.4.6 Optical Interfaces 3489.4.7 Polymer Material Applications 3489.5 Benefits for Next Generation Systems 3499.5.1 Harmonized Approach for Component to System Protection 3499.5.2 IEC Specification Requirements 3509.5.3 Cost of System Protection 351Acknowledgments 351References 35110 Co-Design Trade-Offs: Balancing Robustness, Performance, and Cost 353Jeffrey C. Dunnihoo10.1 Co-Designing across Functional and Corporate Boundaries 35310.1.1 Component (Factory) versus System (End User) ESD Issues 35310.1.2 Probabilities and Uncertainties of System ESD Costs 35410.1.3 Bounded and Cumulative ESD Failure Probability 35510.1.4 Product and Organizational Response to ESD Failure 35710.1.5 The Reality of the “Real Cost of ESD” 35810.1.6 Co-Designing a Solution 35810.2 ESD Goals and Constraints 35910.2.1 The Co-Design Gamut 35910.2.2 ESD Margin Requirement Based on Unknown Probabilities 36010.2.3 Extreme and Abusive Users 36110.2.4 Ignoring the “Long Tail” Events 36310.2.5 Capturing Quantitative System Fault Data 36410.2.6 ESD Sousveillance 36410.2.7 Beyond ESD Sousveillance 36510.2.8 Vulnerabilities in the Meantime 36510.3 Costs of System and Component ESD Susceptibility 36610.3.1 Poor User Experience 36610.3.2 Quantifying User Experience 36710.3.3 Failure Analysis and Customer Return Costs 36710.4 Costs of Improving System and Component ESD Robustness 36910.4.1 Component Costs 36910.4.2 Reduced Profit Margin 37010.4.3 Reduced Performance 37010.4.4 Co-Design Cost Allocation Example 37110.4.5 Alternative Cost Reductions with Performance Enhancement 37210.4.6 Increased Time-to-Market and Negative TVS Pricing 37510.5 Defining the Interaction and Trade-off Matrix 37610.5.1 Performance 37610.5.2 Price 37710.5.3 Robustness 37710.6 Assigning the Costs of Failure Criteria 37810.7 System Development Triangle Co-Design Contributions 37910.7.1 Function Vendor Partitions (CPU, ASIC, Interface Device) 38010.8 Product Planning Guidelines 38010.8.1 Set Realistic Robustness Goals Early 38010.8.2 Responsibilities of the Product Design Team 38110.8.3 Responsibilities of the Product Testing and Qualification Team 38110.8.4 Responsibility for Line Returns from Manufacturing 38110.8.5 Responsibility for Field Returns from the Customer 38110.8.6 Organizational Interaction with Vendors 38110.9 Validating Co-Design Trade-off Decisions 38210.9.1 Historical Data Availability 38210.9.2 Difficulties of Cost Identification and Assignment 38310.9.3 Dangers of the “Keep Your Head Down” Mentality 38410.9.4 Balancing Low-Level Problems with High-Profile Exposure 38510.10 Conclusions on Co-Design Economics 387References 387Glossary 389Index 391