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The more rapid rate of increase in the speed of microprocessor technology than in memory speeds has created a serious 'memory gap' for computer designers and manufacturers. High Performance Memory Systems addresses this issue and examines all aspects of improving the memory system performance of general-purpose programs. Current research highlights from both industry and academia focus on: coherence, synchronization, and allocation; power-awareness, reliability, and reconfigurability; software-based memory tuning; architecture design issues; and workload considerations. Topics and features: Both hardware and software approaches to scalability and speed disparities are consideredIntroductory chapter provides broad examination of high performance memory systemsIncludes coverage of topics from several important international conferences.Edited by leading international authorities in the field, this new work provides a survey from researchers and practitioners on advances in technology, architecture, and algorithms that address scalability needs in multiprocessors and the expanding gap between CPU/network and memory speeds.It is ideally suited to researchers and R & D professionals with interests or practice in computer engineering, computer architecture, and processor architecture.
1 Introduction to High-Performance Memory Systems — scan all.- 1.1 Coherence, Synchronization, and Allocation.- 1.2 Power-Aware, Reliable, and Reconfigurable Memory.- 1.3 Software-Based Memory Tuning.- 1.4 Architecture-Based Memory Tuning.- 1.5 Workload Considerations.- I Coherence, Synchronization, and Allocation.- 2 Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors.- 3 Dynamic Verification of Cache Coherence Protocols.- 4 Timestamp-Based Selective Cache Allocation.- II Power-Aware, Reliable, and Reconfigurable Memory.- 5 Power-Efficient Cache Coherence.- 6 Improving Power Efficiency with an Asymmetric Set-Associative Cache.- 7 Memory Issues in Hardware-Supported Software Safety.- 8 Reconfigurable Memory Module in the RAMP System for Stream Processing.- III Software-Based Memory Tuning.- 9 Performance of Memory Expansion Technology (MXT).- 10 Profile-Tuned Heap Access.- 11 Array Merging: A Technique for Improving Cache and TLB Behavior.- 12 Software Logging under Speculative Parallelization.- IV Architecture-Based Memory Tuning.- 13 An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems.- 14 Bandwidth-Based Prefetching for Constant-Stride Arrays.- 15 Performance Potential of Effective Address Prediction of Load Instructions.- V Workload Considerations.- 16 Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems.- 17 Evaluation of Large L3 Caches Using TPC-H Trace Samples.- 18 Exploiting Intelligent Memory for Database Workloads.- Author Index.
Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk, St. Louis) Franklin, Mark A. (Washington University, Washington University in St. Louis) Crowley, Patrick (Associate Professor, Computer Science & Engineering, New York) Hadimioglu, Haldun (Polytechnic University, Inc.) Onufryk, Peter Z. (Integrated Device Technology
Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk, St. Louis) Franklin, Mark A. (Washington University, Washington University in St. Louis) Crowley, Patrick (Associate Professor, Computer Science & Engineering, New York) Hadimioglu, Haldun (Polytechnic University, Inc.) Onufryk, Peter Z. (Integrated Device Technology, Patrick Crowley, Mark A. Franklin