ASIC and FPGA Verification

A Guide to Component Modeling

Häftad, Engelska, 2004

Av Richard Munden, Free Model Foundry) Munden, Richard (CEO

849 kr

Beställningsvara. Skickas inom 7-10 vardagar

Fri frakt för medlemmar vid köp för minst 249 kr.

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

Produktinformation

Utgivningsdatum2004-10-23
Mått191 x 235 x 24 mm
Vikt860 g
SpråkEngelska
SerieSystems on Silicon
Antal sidor336
FörlagElsevier Science & Technology
EAN9780125105811

Du kanske också är intresserad av

Customizable Embedded Processors

Paolo Ienne, Rainer Leupers

979 kr

VHDL-2008

Peter J. Ashenden, Jim Lewis, Australia) Ashenden, Peter J. (Adjunct Associate Professor, School of Computer Science, University of Adelaide, U.S.A.) Lewis, Jim (Chairman, IEEE Working Group on VHDL,<br>SynthWorks Design, Inc., Tigard, OR

819 kr

Network Processors

Ran Giladi

1 259 kr

Del 1

Reconfigurable Computing

Scott Hauck, Andr� DeHon, André DeHon, André Dehon

1 259 kr

The System Designer's Guide to VHDL-AMS

Peter J. Ashenden, Gregory D. Peterson, Darrell A. Teegarden

1 419 kr

On-Chip Communication Architectures

Sudeep Pasricha, Nikil Dutt

1 119 kr

Del 2

Embedded DSP Processor Design

Dake Liu

1 209 kr

System Level Design with Rosetta

Perry Alexander

1 129 kr

The Student's Guide to VHDL

Peter J. Ashenden, Australia) Ashenden, Peter J. (Adjunct Associate Professor, School of Computer Science, University of Adelaide

589 kr

Del 3

The Designer's Guide to VHDL

Peter J. Ashenden, Australia) Ashenden, Peter J. (Adjunct Associate Professor, School of Computer Science, University of Adelaide, Peter J Ashenden

969 kr

Tillhör följande kategorier

Systemvetenskap och AI inom Data och it

1.Introduction to Board-Level Verification; 2.Tour of a simple model; 3.VHDL packages for component models; 4.Introduction to SDF; 5.Anatomy of a VITAL Model; 6.Modeling Delays; 7.VITAL truth tables; 8.Modeling timing constraints; 9.Modeling registered devices; 10.Conditional delays and timing constraints; 11.Negative timing constraints; 12.Timing Files and Backannotation; 13.Adding Timing to Your RTL Code; 14.Modeling Memories; 15.Considerations for Component Modeling; 16.Modeling Component Centric Features; 17.Testbenches for Component Models

Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible—the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.—Randy Harr, Sevni TechnologyThis book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.—Hardy Pottinger, University of Missouri-Rolla