Off-Chip Memory Access Optimization

Computationally expensive applications involve large amount of data and need to store them in cheap and large capacity off-chip memories. Each processor in multi-core system frequently accesses the global memory which takes many cycles (latency) for the transfer of data. Latency in digital systems has become a critical parameter. An important class of digital systems includes applications such as video image processing which is extremely memory expensive. In such applications, a significant amount of delay and power is consumed during memory access especially for off-chip dynamic random access memories (DRAMs). We need accurate methods for modeling and optimizing inter-core memory operations.This book describes techniques like Memory Delay Modeling, memory allocation and slack time management for optimizing memory access latency for data intensive applications.