Low Power Mixed-Mode Circuit Design of Sar Adc

In this book a novel model for power consuming in the mixed signal system is presented. In the proposed model a power profile of the mixed signal versus frequency is shown and the impacts of the analog and the digital sub sections are determined. The presented model is applied on the 6 bit SARADC. A primary low power 6 bit SARADC is designed for WSN applications. Presented model shows that the impact of analog section in the lower range of frequencies is more than digital section. Optimizing this block, results in over 100% power consumption reduction in the optimized SAR ADC.