Guide to Computer Processor Architecture

This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined,multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) codein C++.This facilitates synthesis and testingon an FPGA-baseddevelopment board (Such a board can be freely obtained from the XilinxUniversity Program targeting university professors). The book can be useful for several reasons. First, it is a novel way tointroduce computer architecture: The codes given can serve as labsfor a processor architecture course. Second, the book content is basedon the RISC-V Instruction Set Architecture, which is an open-sourcemachine language promising to become the main machine language to be taught,replacing DLX and MIPS. Third, all the designs are implemented throughthe HLS tool, which is able to translate a C program intoan intellectual property (IP). Lastly,HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willingto implement processors on FPGA, as well as researchers willing to developRISC-V based hardware simulators. Bernard Goossensis Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer,Architecture et microarchitecture des processeurs, 2002.